G01R31/2656

Opto electrical test measurement system for integrated photonic devices and circuits

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

Photocurrent scanning system

A photocurrent scanning system comprises a laser generating device, a focusing device, a displacement adjustment device, a bias supply device, and a measuring device. The laser generating device is used to emit a laser. The focusing device is used to focus the laser to a surface of a sample. The displacement adjustment device is used to place the sample and adjust a position of the sample, to make the laser focused onto different parts of the surface of the sample. The bias supply device is used to supply a voltage to the sample. The measuring device is used to measure a photocurrent signal flowing through the sample.

INSPECTION APPARATUS AND INSPECTION METHOD
20210356405 · 2021-11-18 ·

This inspection apparatus is for inspecting an inspection subject device. The inspection subject device is formed on an object to be inspected, and is a reverse-side irradiation-type imaging device into which light enters from the reverse side opposite to the side where a wiring layer is provided. This inspection apparatus has: a placement table having a transparent surface on which the object to be inspected is placed; a light irradiation mechanism that is provided in the placement table and that irradiates the to-be-inspected object placed on the placement table with light through the placement surface; and an acquisition unit that acquires in-plane distribution of illuminance of light from the placement table.

Terahertz Plasmonics for Testing Very Large-Scale Integrated Circuits under Bias

Various embodiments are described that relate to failure determination for an integrated circuit. An integrated circuit can be tested to determine if the integrated circuit is functioning properly. The integrated circuit can be subjected to a specific radiation such that the integrated circuit produces a response. This response can be compared against an expected response to determine if the response matches the expected response. If the response does not match the expected response, then the integrated circuit fails the test. If the response matches the expected response, then the integrated circuit passes the test.

OPTICAL SYSTEMS AND METHODS OF CHARACTERIZING HIGH-K DIELECTRICS
20220003678 · 2022-01-06 ·

The disclosed technology generally relates to characterization of semiconductor structures, and more particularly to optical characterization of high-k dielectric materials. A method includes providing a semiconductor structure comprising a semiconductor and a high-k dielectric layer formed over the semiconductor, wherein the dielectric layer has electron traps formed therein. The method additionally includes at least partially transmitting an incident light having an incident energy through the high-k dielectric layer and at least partially absorbing the incident light in the semiconductor. The method additionally includes measuring a nonlinear optical spectrum resulting from the light having the energy different from the incident energy, the nonlinear optical spectrum having a first region and a second region, wherein the first region changes at a different rate in intensity compared to the second region. The method further includes determining from the nonlinear optical spectrum one or both of a first time constant from the first region and a second time constant from the second region, and determining a trap density in the high-k dielectric layer based on the one or both of the first time constant and the second time constant.

TEST OF AN EXAMINATION TOOL
20210341559 · 2021-11-04 ·

There is provided a system and a method of testing an optical device in a scanner for scanning a semiconductor specimen, the method comprising controlling, by a processor and memory circuitry (PMC) operatively connected to the scanner, an optical element optically connected to the optical device to deviate an optical path of light transmitted by the optical device so to transmit towards an imaging sensor, thereby enabling acquiring, by the imaging sensor, image data informative of the optical device, wherein in a scanning mode the optical element enables light transmitting from the optical device towards another optical device comprised in the scanner, and processing the acquired image data to obtain results informative of operability of the optical device.

Efficient laser-induced single-event latchup and methods of operation

Systems and methods are provided for testing a threshold energy required to cause a latchup on an electronic component. An exemplary method includes applying a series of laser pulses to a testing object with a pulsed laser unit. The testing object is connected to a testing circuit which can measure the energy of each of the series of laser pulses, and detect whether a pulse of the series of laser pulses resulted in a latchup on the testing object. Upon detecting the pulse, the method provides for logging the energy of the pulse using a recording unit and logging the latchup status of the test device. If a latchup is detected, the testing circuit automatically mitigates the latchup event.

SEMICONDUCTOR FAILURE ANALYSIS DEVICE AND SEMICONDUCTOR FAILURE ANALYSIS METHOD
20230072615 · 2023-03-09 · ·

A semiconductor failure analysis device includes an analysis part that analyzes a failure place in a semiconductor device; a marking part that irradiates the semiconductor device with laser light; a device arrangement part in which a wafer chuck, which holds the semiconductor device and on which an alignment target is provided, moves relative to the analysis part and the marking part; and a control part that outputs commands. The control part moves the wafer chuck to a position at which the analysis part is capable of taking an image of the alignment target, then outputs an alignment command that causes the marking part to be aligned with the analysis part with the alignment target as a reference, and irradiates the semiconductor device with laser light in a state in which a positional relationship between the marking part and the analysis part is maintained.

WAFER METROLOGY TECHNOLOGIES
20220413029 · 2022-12-29 ·

Various approaches can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. Certain approaches employ Second Harmonic Generation and in some cases may utilize pump and probe radiation. Other approaches involve determining current flow from a sample illuminated with radiation. Decay constants can be measured to provide information regarding the sample. Additionally, electric and/or magnetic field biases can be applied to the sample to provide additional information.

EFFICIENT LASER-INDUCED SINGLE-EVENT LATCHUP AND METHODS OF OPERATION
20220390511 · 2022-12-08 ·

Systems and methods are provided for testing a threshold energy required to cause a latchup on an electronic component. An exemplary method includes applying a series of laser pulses to a testing object with a pulsed laser unit. The testing object is connected to a testing circuit which can measure the energy of each of the series of laser pulses, and detect whether a pulse of the series of laser pulses resulted in a latchup on the testing object. Upon detecting the pulse, the method provides for logging the energy of the pulse using a recording unit and logging the latchup status of the test device. If a latchup is detected, the testing circuit automatically mitigates the latchup event.