According to one embodiment, an electronic circuit includes: a current supply circuit, a detection circuit, a timing generation circuit, a sample hold circuit and a calculation circuit. The current supply circuit supplies a sine wave current for measurement to a gate terminal of a semiconductor switching device. The detection circuit detects a sine wave voltage generated in response to supply of the sine wave current to generate a detection signal. The timing generation circuit counts cycles of the sine wave voltage. The sample hold circuit samples the detection signal at a timing depending on a count value of the timing generation circuit. The calculation circuit calculates a gate resistance of the semiconductor switching device based on the sampled voltage.

The invention provides a method for checking a semiconductor switch for a fault, wherein the semiconductor switch is driven with a PWM signal with a variable duty cycle. To the benefit of determining faults on the semiconductor switch reliably and cost-effectively, it is provided that if the semiconductor switch is operated with a duty cycle of 100% or 0%, the current measurement of the overall system is evaluated, while if the semiconductor switch is operated with a duty cycle of between 0% and 100%, the generated voltage pulses across the semiconductor switch are evaluated.

Embodiments relate to testing a plurality of LEDs by applying a voltage difference between anode electrodes and cathode electrodes of the plurality of LEDs using transistors and probe pads on a display substrate. The anode electrodes of the plurality of LEDs are connected to a first probe pad via clamping transistors, and the cathode electrodes are connected to a second probe pad. Responsive to applying the voltage difference, it is determined whether the plurality of LEDs satisfy a threshold level of operability. The display substrate also includes driving transistors and switching transistors connected to the plurality of LEDs, the driving transistors and switching transistors used during operating mode.

The invention is a test system for testing silicon wafers or packaged devices. The system includes a tester having multiple testing stacks that each hold a vertical stack of test engines, data buffers, pin drivers, and other resources, which are electrically connected on one side to a wafer or DUT and on the other side to a test host computer via fast data links. Each testing stack is disposed on a top side of a wafer contactor electrically connected to a wafer or a load board electrically connected to a DUT. The system includes a cooling system to remove heat during operation. The system minimizes the data signal path between the pads of the devices being tested and the pin drivers of the tester, the test engines, and the test host computer. High performance is possible by the connection of bottom of each testing stack directly to the wafer contactor.

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

Embodiments relate to testing a plurality of LEDs by applying a voltage difference between anode electrodes and cathode electrodes of the plurality of LEDs using transistors and probe pads on a display substrate. The anode electrodes of the plurality of LEDs are connected to a first probe pad via clamping transistors, and the cathode electrodes are connected to a second probe pad. Responsive to applying the voltage difference, it is determined whether the plurality of LEDs satisfy a threshold level of operability. The display substrate also includes driving transistors and switching transistors connected to the plurality of LEDs, the driving transistors and switching transistors used during operating mode.

An apparatus for predicting a future state of an electronic component is provided. The apparatus includes a measuring unit configured to measure a waveform of a signal related to the electronic component. Further, the apparatus includes a processing unit configured to calculate a predicted value of a characteristic of the electronic component based on a reliability model of the electronic component using the waveform of the signal.

A method includes loading the semiconductor structure on a stage; providing a detector disposed above the semiconductor structure and the stage; applying a voltage to the semiconductor structure; identifying a portion of the semiconductor structure at a temperature substantially greater than a predetermined threshold by the detector; rotating the stage and recording a rotation of the stage after identifying the portion of the semiconductor structure; and deriving a position of the portion of the semiconductor structure based upon the rotation of the stage.

A method for determining an emission coefficient of a device under test (DUT) using a test circuit is disclosed. The method comprises coupling a parameter measurement circuit associated with the test circuit to an input pin associated with the DUT, wherein the input pin is coupled to a diode element within the DUT and performing voltage and current measurements associated with the input pin using the parameter measurement circuit. In some embodiments, the method further comprises determining a plurality of contact resistance values respectively based on the voltage and current measurements and an emission coefficient estimate using a contact resistance estimation circuit; and determining an emission coefficient associated with the DUT based on the determined plurality of contact resistance values using an emission coefficient determination circuit.

A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.