In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.

Machine with flying probes for testing electronic boards comprising a conveyor for loading/unloading the boards into/from the testing station, a plurality of flying probes suitable to interact with predetermined points of each board and a plurality of contacting devices arranged at the sides of the working volume of the flying probes and suitable to cooperate with contact areas arranged on one edge of the board.

A method for testing. An external clock frequency is generated. Test data is supplied over a plurality of SSI connections clocked at the external clock frequency, wherein the test data is designed for testing a logic block. A DSTA module is configured for the logic block that is integrated within a chip to a bandwidth ratio, wherein the bandwidth ratio defines the plurality of SSI connections and a plurality of PSI connections of the chip. The external clock frequency is divided down using the bandwidth ratio to generate an internal clock frequency, wherein the bandwidth ratio defines the external clock frequency and the internal clock frequency. The test data is scanned over the plurality of PSI connections clocked at the internal clock frequency according to the bandwidth ratio, wherein the plurality of PSI connections is configured for inputting the test data to the plurality of scan chains.

Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.

An integrated circuit chip comprising: system circuitry comprising interconnect circuitry for transporting transactions; and monitoring circuitry configured to: monitor transactions from the interconnect circuitry comprising transactions between an entity and a specified region of the integrated circuit chip, the entity being associated with a set of one or more access rights for accessing the specified region of the integrated circuit chip; determine from the monitored transactions values of one or more parameters associated with the access to the specified region by the entity to identify whether the entity has breached its access rights; and perform a dedicated action indicative of a breach of the access rights in response to determining from the parameter values that the entity has breached its access rights.

The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and linking a printed circuit board (PCB) block to a physical layout associated with the electronic design. Embodiments may further include receiving, at a layout environment, at least one simulation parameter and performing, using a finite difference time domain (FDTD) simulator, a time-domain simulation, based upon, at least in part, the at least one simulation parameter.

Various aspects of the disclosed technology relate to techniques of selecting scan cells from state elements for partial scan designs. Signal probability values for logic gates in a circuit design are first determined. Based on the signal probability values, next-state capture probability values for state elements in the circuit design are computed. Based on the next-state capture probability values, scan cells are selected from the state elements. Scan cells may be further selected based on continuously-updated control weight values and observation weight values associated with the state elements.

A pad/trace line layout for a PMR writer structure having two or more writers on a slider, and a process for selecting the best of the multiple writers is disclosed. Each writer is individually probed with a spin stand test device to generate performance results including bit error rate (BER), and area density capability (ADC). After the best writer is determined, the slider is integrated in a HGA. Only the best writer is connected through trace lines to a preamp to enable functionality. At least one trace line has a plurality of arms that enable flexibility in connecting the best writer to the preamp while other arms are not connected. In some embodiments, all writers share a common W pad that is connected to the preamp through one of two trace lines while the other trace line has one of the plurality of arms connected to the best writer.

A method for testing. The method includes sending a single instruction over a JTAG interface to a JTAG controller to select a first internal test data register of a plurality of data registers. The method includes programming the first internal test data register using the JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level.

A method of debugging a printed circuit board with at least one boundary-scan compliant device is presented. The method uses an electronic processing unit and includes the steps of: retrieving boundary-scan properties of the at least one boundary-scan compliant device, the properties including a listing of boundary-scan compliant circuit terminals of the at least one boundary-scan compliant device; retrieving connectivity properties; selecting and displaying a circuit graph of at least a part of the devices mounted on the printed circuit board, the circuit graph including at least one of the devices mounted on the printed circuit board and a least one further device from the devices which has a circuit terminal interconnected to a circuit terminal of the device for visualizing at least the device, the further device and interconnects between the circuit terminals of the devices.