Dynamically monitoring of an electrically-isolated power bus for a DC power system is described, and includes dynamically monitoring voltage and current on the power bus to determine a variation in the voltage on the power bus. When the variation in the voltage on the power bus is less than a threshold, an active positive isolation resistance term and an active negative isolation resistance term are determined. A first voltage balance term is determined based upon a ratio of the active positive isolation resistance term and the active negative isolation resistance term. A dynamic positive isolation resistance term and a dynamic negative isolation resistance term are determined based upon the active negative isolation resistance term. A fault associated with the power bus is determined based upon the dynamic positive isolation resistance term and the dynamic negative isolation resistance term.

Embodiments described herein relate to a system. The system may include a base configured to be removably coupled to an electrical component. The base may include a first plurality of crossbar alignment features arranged in a first pattern. The system may also include a crossbar configured to be removably coupled to the base using a portion of the first plurality of crossbar alignment features. The crossbar may include a first plurality of adapter plate alignment features arranged in a second pattern. The system may also include an adapter plate configured to be removably coupled to the crossbar using a subset of the first plurality of adapter plate alignment features. The adapter plate may include a plurality of measurement device mounting features.

A first aspect of the present invention will provide a short circuit detector, including: a voltage detection circuit to detect gate voltage which is input from a gate driving circuit to the semiconductor element; and a short circuit detection circuit to detect a short circuit state of the semiconductor element, when gate voltage of the semiconductor element becomes higher than or equal to first reference voltage in a transition period from when a turn-on signal is input to the gate driving circuit until when a mirror period of the semiconductor element starts.

A circuit for detection and warning of electro-migration in a region on a printed circuit board between a first electrically conductive element having a first electrical characteristic and a second electrically conductive element having a second electrical characteristic different than the first. The circuit includes an electrically conductive guard track that is electrically isolated from the first and second elements in the region and has a normal condition electrical characteristic based on the first and second characteristics. The circuit includes an electrical characteristic supervisor to detect an electrical characteristic of the guard track. In response to electro-migration creating an electrical connection of the guard track to the first or second element, the guard track has an abnormal condition electrical characteristic different than the normal condition. In response to detecting the abnormal condition of the guard track, the supervisor effectuates a warning of electro-migration in the region.

The disclosure relates to a test system for improving test stability. One end of the connection pin is fixed to a bottom surface of a corresponding pin socket, the bottom surface is near an end of the plug end, the other end of each connection pin is disposed in the corresponding pin socket and a portion of the other end of the connection pin protrudes from a top surface of an end of the plug end. The connection pin in the plug end will not be deformed by external force, which can avoid the deformation of the connection pin caused by external force, and ensure the electrical connection and test stability.

An integrated circuit (IC) includes functional logic therein that can be enabled by application of a predefined thermal cycle. The IC includes an enabling fuse operatively coupled to the functional logic, the functional logic being disabled unless enabled by activation of the enabling fuse. A set of thermal sensors are arranged in a physically distributed manner through at least a portion of the IC. A test control macro operatively couples to the set of thermal sensors and the enabling fuse for activating the enabling fuse to enable the functional logic in response to application of a thermal cycle that causes the set of thermal sensors to sequentially experience a thermal condition matching a thermal sequence enabling test. A related method and system for applying the predefined thermal cycle are also provided.

Embodiments described herein relate to a system. The system may include a base configured to be removably coupled to an electrical component. The base may include a first plurality of crossbar alignment features arranged in a first pattern. The system may also include a crossbar configured to be removably coupled to the base using a portion of the first plurality of crossbar alignment features. The crossbar may include a first plurality of adapter plate alignment features arranged in a second pattern. The system may also include an adapter plate configured to be removably coupled to the crossbar using a subset of the first plurality of adapter plate alignment features. The adapter plate may include a plurality of measurement device mounting features.

A self-check system and a method thereof are disclosed. In the self-check system, a memory stores a safety check program, a main application program and a predetermined checksum data. The safety check program include a circuit check program, a watchdog circuit reset program and a checksum check program. When a chip system is powered on, a processing unit executes the main application program, and then executes an interrupt call to generate an interrupt, so as to execute the safety check program and the circuit check program to check a to-be-checked circuit. The processing unit also executes the watchdog circuit reset program to reset a counting value of a watchdog circuit. The processing unit also executes the checksum check program to calculate a checksum data of the first safety check program, and reset the chip system when the calculated checksum data is not equal to the predetermined checksum data.

Disclosed is a test system for testing electric connections, in particular soldered connections, between electronic components and a printed circuit board to be tested, characterized in that the test system includes a subassembly, which is movably mounted in a housing of the test system, and a current and/or voltage source for energizing the circuit board to be tested, the current and/or voltage source being arranged in the housing of the test system in such a way as to be movable in at least two directions in space.

A method of measuring electromagnetic interference (EMI) to noninvasively identify component degradation or failure in power electronics circuitry. The method involves characterizing the degradation or failure characteristics of the component and modeling those characteristics to enable a machine learning algorithm to identify EMI frequency distribution characteristics that correspond to the degradation or failure. The EMI frequency distribution is measured and the data provided to the machine learning algorithm whereupon the algorithm identifies degradation or failures indicated by the measured data.