A high temperature fixture, said fixture comprising: at least three noble metal electrodes arranged in parallel, among which two adjacent noble metal electrodes are used for clamping a test sample; noble metal wires connected to the noble metal electrodes at one end, and to a test device at the other end for transmitting test signals generated by the test sample to the test device through the noble metal electrodes; and a thermocouple for measuring the temperature of the test materials.

The Power Line Fault Locating System is a means of locating faults in a utility power system by sampling the noise at multiple positions around the system and correlating and summing the resulting data. When the processed data produces a spike, a noise source has been detected. The position of the spike in the data will indicate the location of the noise source with great precision. With three of more receivers the location of the fault can be determined in two dimensions. The invention can operate on both continuous noise resulting from minor flaws in the power system as well as the noise burst resulting from a power system failure. Noise resulting from minor flaws may come from slack line fittings, electrical leakage in insulators or at poles. A burst of noise may come from insulator flash over, lightning strike, or something contacting a power line.

A first aspect of the present invention will provide a short circuit detector, including: a voltage detection circuit to detect gate voltage which is input from a gate driving circuit to the semiconductor element; and a short circuit detection circuit to detect a short circuit state of the semiconductor element, when gate voltage of the semiconductor element becomes higher than or equal to first reference voltage in a transition period from when a turn-on signal is input to the gate driving circuit until when a mirror period of the semiconductor element starts.

A directional pulse injection system and method are described for injecting a pulse into a microelectronic system for electrostatic test. One example has a transformer coupled to a pulse source through a transmission line and to a conductive trace of a test board to apply the electrical pulse to the trace as a test pulse. The test board is connected to a microelectronic device under test. This example also has a cancellation pulse transmission line coupled to the pulse source and a cancellation pulse contact coupled to the pulse source through the cancellation pulse transmission line and to the trace on a side of the trace opposite the transformer to receive a cancellation signal from the pulse source and to couple the cancellation signal to the trace to cancel a portion of the test pulse.

A signal testing apparatus for a printed circuit board is disclosed which includes a plurality of input terminals for receiving an external testing signal, a plurality of output terminals for supplying the printed circuit board with the external testing signal, a plurality of switches arranged between the plurality of input terminals and the plurality of output terminals for controllably coupling the plurality of input terminals to the plurality of output terminals, an ammeter for measuring a magnitude of a current on a first path provided by the coupling of the plurality of switches, and a voltmeter for measuring a magnitude of a voltage on a second path provided by the coupling of the plurality of switches.

Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

Described embodiments include a fault monitoring system comprising a fault logic circuit having a fault logic input adaptable to be coupled to sensor inputs, and first and second fault logic outputs. The fault logic circuit compares a plurality of data values provided by respective sensor inputs to respective fault thresholds, and provides respective fault signals at the first fault logic output responsive to a fault event in which a respective data value exceeds its respective fault threshold. A timer has a timer input coupled to the reset output, and a timer output. A data register has a first data register input coupled to the write control output, a second data register input coupled to the timer output, and a data register output. The data register receives fault data that includes an event identifier, a timer value, and a timer expiration indicator.

Techniques are disclosed to determine the temperature-dependent insertion loss and propagation delay of traces in a printed circuit board design. For example, an example method includes determining a first temperature at a first portion of a trace of a PCB design based on a thermal map of the PCB design. The method further includes determining a second temperature at a second portion of the trace based on the thermal map. The method further includes calculating a temperature-dependent property of the PCB at the first portion based on the first temperature. The method further includes calculating the temperature-dependent property of the PCB at the second portion based on the second temperature. The method further includes calculating at least one of a signal loss and propagation delay on the trace based on the temperature-dependent property of the PCB at the first portion and the second portion.

Systems for reliability testing include a picometer configured to measure a leakage current across a device under test (DUT); a camera configured to measure optical emissions from the DUT based on a timing of the measurement of the leakage current; and a test system configured to apply a stress voltage to the DUT and to correlate the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

A directional pulse injection system and method are described for injecting a pulse into a microelectronic system for electrostatic test. One example has a transformer coupled to a pulse source through a transmission line and to a conductive trace of a test board to apply the electrical pulse to the trace as a test pulse. The test board is connected to a microelectronic device under test. This example also has a cancellation pulse transmission line coupled to the pulse source and a cancellation pulse contact coupled to the pulse source through the cancellation pulse transmission line and to the trace on a side of the trace opposite the transformer to receive a cancellation signal from the pulse source and to couple the cancellation signal to the trace to cancel a portion of the test pulse.