A self-check system and a method thereof are disclosed. In the self-check system, a memory stores a safety check program, a main application program and a predetermined checksum data. The safety check program include a circuit check program, a watchdog circuit reset program and a checksum check program. When a chip system is powered on, a processing unit executes the main application program, and then executes an interrupt call to generate an interrupt, so as to execute the safety check program and the circuit check program to check a to-be-checked circuit. The processing unit also executes the watchdog circuit reset program to reset a counting value of a watchdog circuit. The processing unit also executes the checksum check program to calculate a checksum data of the first safety check program, and reset the chip system when the calculated checksum data is not equal to the predetermined checksum data.

A circuit interrupter includes a sensor structured to output a sensor signal, a control unit structured to receive an external control signal, the control unit including: a communication interface structured to receive the external control signal, and a waveform generator structured to generate a waveform equivalent to the sensor signal in response to the external control, and a signal processing circuit structured to receive and process the sensor signal or the generated waveform and to output the processed sensor signal or generated waveform to the control unit.

Disclosed herein are embodiments of systems, methods, and products to automatically and intelligently generate a test bench to test an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) design. A computer may receive netlist of the IC design forming a device under test (DUT). From the DUT, the computer may extract and/or calculate one or more parameters. Based on the one or more parameters, the computer may generate a test bench comprising a resistance inductance capacitance (RLC) circuit to provide ESD stimulus to the DUT. The ESD stimulus and therefore the test bench may be based on a human body model (HBD) or a charged device model (CDM). In case of the CDM, the computer may allow a circuit designer to select or deselect package parameters for testing the ESD protection circuit.

A battery pack simulation device includes an input unit that receives voltage values, current values, temperature, and initial impedance values, an output value generation unit that generates an output value based on the input voltage value, current value, temperature, and initial impedance value, an output unit that transmits the generated output value to the battery management unit, and a monitoring unit that monitors the operation of the battery management unit.

Systems and methods for testing a lightning protection circuit are provided. Aspects include providing an alternating current (AC) test signal source coupled to a circuit under test, the circuit under test comprising a lightning protection circuit having a threshold voltage, a first filter, and a second filter, providing a direct current (DC) voltage supply in series with a filtering device, the filtering device coupled to the AC test signal source, providing a first capacitor coupled between the AC test signal source and the circuit under test, operating the DC voltage supply and the AC test signal source to provide a first test signal to the circuit under test, wherein the first test signal comprise a first voltage that exceeds the threshold voltage, measuring a first impedance of the circuit under test responsive to providing the first test signal, wherein the first impedance corresponds to the first filter.

An electric power measuring device, consisting of a casing, which is provided with a first end, a second end, and a first through hole; a detection circuit board, which is mounted within the casing, and a switch and an indicator light set are mounted on the detection circuit board; an input pin set, which is mounted on the circuit board, moreover, a contact end of the input pin set passes through the area at the first end and is exposed external of the casing; an output pin set, which is contained within the casing and positioned at the second end; and a coil, which is mounted within the casing and encircles the first through hole. In addition, two ends of the coil are respectively connected to any one of the pins of the input pin set and any one of the pins of the output pin set.

A ground fault circuit interrupter device includes a switch module having a reset switch, a control switch mechanically linked to the reset switch, a ground fault detection module, a self-testing module and a tripping module. The switch module controls the electrical connection between the input and output ends of the device. The ground fault detection module detects a leakage current signal at the output end. The self-testing module is coupled to the ground fault detection module and periodically generates a self-test pulse signal which simulates the leakage current signal. The tripping module is electrically coupled to the ground fault detection module and mechanically coupled to the switch module and the control switch, to control the movement of the switch module and the control switch. The control switch, which opens and closes at the same time as the reset switch, controls the power supply to the self-testing module.

A testing system for imposing a traveling wave signal on an electric power system signal for testing a fault detector is disclosed herein. The testing system may be configured to simulate a fault at a simulated location by controlling the timing of the traveling wave signal. The testing system may be configured to impose multiple traveling wave signals to test the accuracy of the fault location determined by the fault detector. The testing system may be configured with multiple testing apparatuses using time coordination and referenced to an intended fault instant. The testing system may be configured to supply traveling waves of different polarities to test for different fault type detection.

Implementations of ground fault circuit interrupter (GFCI) self-test circuits may include: a current transformer coupled to a controller, a silicon controlled rectifier (SCR) test loop coupled to the controller, a ground fault test loop coupled to the controller, and a solenoid coupled to the controller. The SCR test loop may be configured to conduct an SCR self-test during a first half wave portion of a phase and the ground fault test loop may be configured to conduct a ground fault self-test during a second half wave portion of a phase. An SCR may be configured to activate the solenoid to deny power to a load upon one of the SCR self-test or the ground fault self-test being identified as failing.

The present invention provides a method for detecting the anti-island protection performance of an inverter. An RLC circuit is serially connected between the inverter and a grid connection switch, the resonant frequency of the RLC load is set as three different numerical values for enabling the same to present resistance, capacitance and inductance, and a time value from the disconnection of the grid connection switch to the operation stop of the inverter under detection is recorded after a fundamental current value of the grid connection switch is set to a different value each time; and weighted calculation is performed on the time value to obtain a test result and grade evaluation of the anti-island protection ability of the inverter. By adoption of the detection method provided by the present invention, the problem that the anti-island protection ability of the photovoltaic inverter is difficult to precisely evaluate is solved; the anti-island protection performance of the inverter is comprehensively and objectively reflected; and meanwhile the phenomenon that a part of inverters cannot correctly reflect the anti-island ability of the inverters with respect to characteristic load design is effectively avoided, a technical support is provided for the existing method for detecting the anti-island protection performance, and related standard systems in the field of detection of the anti-island protection performance are further enriched and perfected.