A circuit board inspection apparatus includes an inspection processing portion that inspects an electric circuit of a board to be inspected, an inspection jig, and a position detector used to position the inspection processing portion relative to the board to be inspected. The inspection jig includes a probe unit having a probe, a first board, a second board located in parallel with the first board in a thickness direction of the first board, an electrical connection portion that electrically connects the first board and the second board, and a second board holding portion that holds the second board from the first board and holds the probe unit on a side opposite to the first board side. The second board holding portion has a position detection opening penetrating in the thickness direction, at a position overlapping the position detector as viewed from the thickness direction of the second board holding portion.

A data processing method that processes a plurality of unit processing data (each unit processing data include plural types of time-series data) includes an evaluation value distribution utilization step, in which processing that uses evaluation value distributions showing degrees of each value of evaluation values obtained by evaluating each time-series datum is carried out (for example, a step in which each time-series datum is compared with reference data and scoring that quantifies results obtained thereby as the evaluation values is carried out, and a step in which judgment of abnormality degrees is carried out using the evaluation value distributions based on results of the scoring); and an evaluation value distribution update step, in which the evaluation value distributions are updated.

An integrated metrology system for evaluating semiconductor wafers, the metrology system comprises a main body that has a rear side and a front side; the front side defines a front border of the main body; one or more detachable supporting units that are detachably coupled to the main body and support the main body while extending outside the front border; and at least one auxiliary supporting unit that is configured to support the main body at an absence of the one or more detachable supporting units

The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch, a second switch, and a third switch. The first switch has a first node coupled to a first device-under-test and a second node coupled to a first signal supply node. The second switch has a first node coupled to the second DUT and a second node coupled to the first signal supply node. The third switch has a first node directly coupled to the first DUT and the second DUT. The third switch has a second node coupled to a second signal supply node. The third switch selectively couples both of the first DUT and the second DUT to the second signal supply node.

A substrate analysis apparatus is provided. The substrate analysis includes: an interlayer conveying module configured to transport a first FOUP; an exchange module which is connected to the interlayer conveying module, and configured to transfer a wafer from the first FOUP to a second FOUP; a pre-processing module configured to form a test wafer piece using the wafer inside the second FOUP; an analysis module configured to analyze the test wafer piece; and a transfer rail configured to transport the second FOUP containing the wafer and a tray containing the test wafer piece. The wafer includes a first identifier indicating information corresponding to the wafer, the test wafer piece includes a second identifier indicating information generated by the pre-processing module which corresponds to the test wafer piece, and the analysis module is configured to analyze the first identifier and the second identifier in connection with each other.

A system is provided for detecting a forcer misalignment, e.g., due to forcer loss of registration (FLR), in a wafer prober used for electrical testing of a semiconductor wafer. The system includes an optical sensor system including a transmitter and receiver affixed to the forcer or to a reference structure (e.g., the prober platen), and a reflector affixed to the other one of the forcer or reference structure. The transmitter emits radiation toward the reflector, which reflects the radiation toward the receiver. The receiver detects the reflected radiation, and generates an output signal indicating the quantity of received radiation. Alignment monitoring circuitry is configured to identify a misalignment of the forcer relative to the reference structure (e.g., platen) based on the output signal generated by the receiver, and in response, output an alert signal, e.g., to suspend operations of the prober and/or display an error notification to an operator.

A wafer test device includes a test interconnect to interface with a microcircuit of the wafer at a first side and an interposer to interface with the test interconnect at a second side of the test interconnect, opposite the first side. The interposer connects the test interconnect, via a printed circuit board (PCB), to a test apparatus that determines and controls test patterns that are applied to the microcircuit via the test interconnect. A support structure supports the test interconnect and the interposer. The support structure includes an inner bearing to tilt the test interconnect to match a tilt of a surface of the microcircuit. An elastomer between the test interconnect and the interposer reduces deflection of the test interconnect during a process of connecting the test interconnect to the microcircuit.

The present application discloses a method for locating an open circuit failure point of a test structure, which includes the following steps: step 1: providing a sample formed with a test structure, a first metal layer pattern and a second metal layer pattern of the test structure forming a series resistor structure through each via; step 2: performing a first active voltage contrast test to the sample to show an open circuit point and making a first scratch mark at an adjacent position of the open circuit point; step 3: forming a coating mark at the first scratch mark on the sample; step 4: performing a second active voltage contrast test to the sample to show the open circuit point and locating a relative position of the open circuit point by using a position of the coating mark as a reference position.

Aspects of the invention include measuring, by a processor, characteristic data of a structure in a first die of a wafer during fabrication, wherein the characteristic data of the structure comprises a current or capacitance measurement in the structure, recording the current or capacitance measurement as an internal chip fingerprint key for the first die, causing, by the processor, completion of fabrication of the first die in the wafer, wherein the first die comprises a hashing engine and a logic lock, generating a die ID for the first die based on the internal chip fingerprint key for the first die, generating a first external key based on the die ID and the hash engine, and inputting the first external key into the first die to unlock the first die, wherein the first external key hashed with the internal chip fingerprint key creates an unlocking key for the logic lock.

A probe card and a wafer testing assembly thereof are provided. The wafer testing assembly includes a printed circuit board, a space transformer, a plurality of copper pillars and a plurality of strengthening structure units. The printed circuit board includes a bottom surface and a plurality of first contacts arranged on the bottom surface. The space transformer includes a top surface and a plurality of second contacts. The second contacts are arranged on the top surface and corresponding to the first contacts. The copper pillars are respectively arranged between the first contacts and the second contacts. Two ends of each of the copper pillars are respectively electrically connected to the first contacts and the second contacts. The strengthening structure units are arranged on the bottom surface of the printed circuit board and respectively surrounding the copper pillars.