A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC.

A method for measuring electron mobility according to the present invention, which is performed by an apparatus comprising a chamber forming a sealed space, an electron gun provided in the chamber, and a metal sample disposed opposite to the electron gun in the sealed space, comprises: an electron irradiation step of irradiating the metal sample with electrons by the electron gun; a sample current measurement step of applying a voltage to the metal sample to measure a sample current obtained in the metal sample according to the applied voltage; a secondary electron current calculation step of calculating a secondary electron current through the measured sample current; and an effective incident current definition step of defining the sum of the measured sample current and the calculated secondary electron current as an effective incident current.

The present disclosure provides an analysis method of a semiconductor device, and the semiconductor device comprises a plurality of HKMG fin field effect transistors and a wafer on which the plurality of HKMG fin field effect transistors are located, and the analysis method comprises: performing acceptance testing on the wafer to be tested; constructing an N-type model based on the position of each N-type transistor at the surface of the wafer to be tested and the corresponding acceptance test result, constructing a P-type model based on the position of each P-type transistor at the surface of the wafer to be tested and the corresponding acceptance test result, and constructing an N/P ratio model corresponding to the surface of the wafer to be tested based on the N-type model and the P-type model; and identifying the N/P ratio model based on a preset standard wafer model to determine whether the wafer to be tested is compliant based on the N/P ratio model. According to the analysis method provided by the present disclosure, it is possible to find a non-compliant wafer among a plurality of wafers, thereby enabling the subsequent targeted parameter analysis and improving the efficiency of optimizing the process scheme.

A flexible probe card according to the present invention includes a compression layer; a transport layer coupled to the compression layer; and a contact layer coupled to the transport layer. The compression layer is formed of encapsulated closed cell polyurethane foam. The transport layer includes connectors for coupling the flexible probe card to a tester. The contact interface layer includes embedded conductive wires placed in a fixed grid pattern in a silicon rubber layer without a specific connector pattern associated either with the transport layer or a device under test.

Embodiments described herein provide a method for identifying failure patterns in electronic devices. The method begins when a limit is determined for a parameter of interest. A series of the electronic devices is then tested using the limit of the parameter of interest. Failing devices are then identified and x and y coordinate values are plotted. Pattern recognition may be used to determine if the failures shown on the coordinate plot fit a failure pattern. The limit of the parameter of interest is then regressed in steps to the mean value of the failing devices and the electronic devices are retested. The failure pattern of the retested devices is examined to determine if the failure pattern fits a failure pattern. If the failure pattern fits a failure pattern then the parameter of interest may be found to affect the yield rate of production for the electronic devices.

A method for use in manufacturing a plurality of electronic devices from a workpiece. The method includes compiling a set of data records in a data file, wherein each data record represents information uniquely associated with a respective electronic device to be manufactured from the workpiece. Based on the data file, deposition of a substance is controlled at selected locations on the workpiece.

There is provided a terahertz device including: a terahertz element configured to generate an electromagnetic wave; a reflection film provided at a position facing the terahertz element and configured to reflect the electromagnetic wave generated from the terahertz element in one direction; and an encapsulating material configured to encapsulate the terahertz element and the reflection film.

A method of preparing an iron-implanted semiconductor wafer for use in surface photovoltage iron mapping and other evaluation techniques. A semiconductor wafer is implanted with iron through the at least two different regions of the front surface of the semiconductor at different iron implantation densities, and the iron-implanted semiconductor wafer is annealed at a temperature and duration sufficient to diffuse implanted iron into the bulk region of the semiconductor wafer.

An object of the present invention is to provide a prober that is able to carry out accurate inspection of semiconductor device in wafer state by reducing the effect of the external noises and the leakage of current and further by eliminating the stray capacitance of the chuck stage against the prober housing. The present invention attains this object by providing a prober comprising a chuck cover conductor that comprises a bottom conductor and a side conductor and an open top, wherein a chuck stage can be contained within a space surrounded by the bottom conductor and the side conductor; an upper cover conductor which has opening through which the conducting support members of the probe for front-side electrodes and the probe for back-side electrodes can be passed, and which is large enough to cover, in a plane view, at least the open top of the chuck cover conductor when the contact member of the probe for front-side electrodes moves relatively within a wafer under inspection; and, a conducting means that brings the chuck cover conductor and the upper cover conductor into contact and makes them electrically continuous.

Metal film thickness can be determined using the sheet resistance, resistivity, and temperature coefficient of resistivity for the metal film. Variation in film thickness measurements caused by resistivity can be reduced or eliminated. A probe head may be used for some of the measurements of the metal film. The probe head can include a temperature sensor used during sheet resistance measurements. A wafer on a chuck is heated, such as using the chuck or the probe head, for the measurements.