A pull out-assisting linkage device for load board of semiconductor automatic test equipment. One end of the handle is rotatably connected to the test equipment by a rotating member. The middle of the handle is bolted to the linkage. The two rotating plates are fixedly connected to the linkage and are located at the two ends of the linkage. Each rotating plate is rotatably connected to the test equipment. Both the first pull out-assisting rod and the second pull out-assisting rod are fixedly connected to each rotating plate by a universal connecting rod. The first pull out-assisting rod and the second pull out-assisting rod are slidingly connected to the test equipment. The first pull out-assisting rod has a first pull out-assisting slot in the side wall, and the second pull out-assisting rod has a second pull out-assisting slot in the side wall, with the first pull out-assisting slot and the second pull out-assisting slot set in reverse. The present invention makes the pull out-assisting device more accurate in propulsion distance, simple in structure, and low in investment cost.

A vector network analyzer is provided which includes a first measuring port, a digital interface connected to the first measuring port, a second measuring port adapted to be connected to a radio frequency (RF) input or output of a device under test (DUT), and a processor. The digital interface is adapted to be connected to a digital input or output of the DUT. The processor is adapted to determine scattering parameters (S-parameters) of the DUT based on measuring signals transmitted to the DUT and received from the DUT by the first measuring port and the second measuring port.

An automated test system for testing singulated electronic components comprises a handler, comprising a plurality of handler pickers and/or spinner pickers, the handler pickers and/or spinner pickers being adapted to each pickup one electronic component, at least one processing station for processing one of the electronic components, a first carrier, a second carrier, and a test unit, for testing singulated electronic components located on a carrier. When the second plurality of electronic components on the second carrier are tested in the test unit while the second plurality of electronic components rest on the second carrier, simultaneously the first carrier is loaded with the first plurality of electronic components by the plurality of handler pickers and/or spinner pickers and/or unloaded from the first plurality of electronic components by the plurality of handler pickers and/or spinner pickers.

The systems and methods described herein are for remaining useful life prediction in electronics and include measuring a plurality of circuit parameters for each of a plurality of circuit components at a plurality of different temperatures, determining a probability density function of failure as a function of time for each of the plurality of circuit components and combining the probability density functions for each of the plurality of circuit components as a function of a circuit that contains the plurality of circuit components.

An automated testing system comprises a high side switch circuit coupled to an input/output (I/O) connection, a low side switch circuit coupled to the I/O connection, a high side force amplifier (HFA) coupled to the high side switch, a low side force amplifier (LFA) coupled to the low side switch, an adjusting circuit coupled to the HFA and the LFA, and a control circuit configured to change the adjusting circuit to change control of current at the I/O connection from one of the HFA or LFA to the other of the HFA or LFA.

Described herein are systems, methods, and other techniques for identifying redundant parameters and reducing parameters for testing a device. A set of test values and limits for a set of parameters are received. A set of simulated test values for the set of parameters are determined based on one or more probabilistic representations for the set of parameters. The one or more probabilistic representations are constructed based on the set of test values. A set of cumulative probabilities of passing for the set of parameters are calculated based on the set of simulated test values and the limits. A reduced set of parameters are determined from the set of parameters based on the set of cumulative probabilities of passing. The reduced set of parameters are deployed for testing the device.

A system for monitoring a circuit, comprising a device under test, such as a power field effect transistor or capacitor, coupled to a power source and a signal source and configured to generate a power output using the signal source, a current output, a voltage output and an end of life detector coupled to the current output and the voltage output and configured to generate a first impedance as a function of the current output and the voltage output, to compare the first impedance to a second impedance and to generate an indicator if the first impedance exceeds the second impedance.

An example test system includes a test head, and a device interface board (DIB) configured to connect to the test head. The DIB is for holding devices under test (DUTs). The DIB includes electrical conductors for transmitting electrical signals between the DUTs and the test head. Servers are programmed to function as test instruments. The servers are external to, and remote from, the test head and are configured to communicate signals over fiber optic cables with the test head. The signals include serial signals.

An automated test equipment (ATE) for testing semiconductor devices, the test equipment comprises a test handler, a spare part, or a contactor socket, and a semiconductor devices tester, The spare part comprises an electronic component for storing and or processing data regarding the spare part or a portion thereof, The test equipment comprises an operator terminal comprising a display or GUI and a data exchange interface which is connected or connectable to the electronic component within the spare part, for at least displaying data stored therein. The ATE further comprises a data buffer unit for buffering the data, a maintenance planning and control unit for planning and controlling maintenance actions of the test equipment, and a dedicated database residing in a control computer.

An automated test equipment for testing one or more DUTs comprises a test head and a DUT interface. The DUT interface comprises a plurality of blocks of spring-loaded pins, for example groups or fields of spring-loaded pins. For example, the DUT interface is configured for establishing an electronic signal path between the test head and a DUT board or load board, which holds the DUT or which provides a connection to the DUT. The automated test equipment is configured to allow for a variation of a distance between at least two blocks of spring-loaded pins.