A method for detecting the aging of a power electronic device that comprises at least one semiconductor component including a step of providing of an excitation signal, which is designed to trigger a flow of an at least approximately semi-sinusoidal excitation current through the semiconductor component in order to introduce a power loss into the semiconductor component, a step of uploading a temperature signal, which represents the temporal course of the temperature of the semiconductor component, and a step of determining of an aging value that represents the aging of the power electronic device by using the temperature signal.

An automatic robot control system and methods relating thereto are described. These systems include components such as a touch screen panel (“TSP”) robot controller for controlling a TSP robot, a camera robot controller for controlling a camera robot and an audio robot controller for controlling an audio robot. The TSP robot operates inside a TSP testing subsystem, the camera robot operates inside a camera testing subsystem, and the audio robot operates inside an audio testing subsystem. Inside the audio testing subsystem, an audio signals measurement system, using a bi-directional coupling, controls the operation of the audio robot controller. In this control scheme, a test application controller is designed to control the different types of subsystem robots. Methods relating to TSP, camera, and audio robots, and their controllers, taken individually or in combination, for automatic testing of device functionalities are also described.

A system for communicatively connecting devices for testing to respective test pins of a test head of an automatic test equipment (ATE). The system includes a tester interface device for communicative connection to the test pins of the ATE. The tester interface device includes a first connector and a second connector. The first connector is communicatively connected by the tester interface device to a first group of the test pins and the second connector is communicatively connected by the tester interface device to a second group of the test pins. The first group and the second group can be different test pins, same test pins, or combinations of some same and some different test pins. The system may also include a first pogo pin block device and a second pogo pin block device.

The interlock detector includes a first input, wherein a first output signal from an interlock generator is applied to the first input. The interlock detector further includes a second output which is configured to provide a microprocessor with a second output signal. The interlock detector further includes a differential amplifier that includes a second input, a third input, and a third output, wherein the second input and the third input are connected to the first input. The interlock detector further includes a comparator circuit that includes a fourth input and a fourth output, wherein the fourth input is connected to the third output, the fourth output is connected to the second output, and the fourth input is positioned between the comparator circuit and the differential amplifier.

A test board includes a first board and a second board. The first board includes a socket on which a device under test (DUT) is mounted, and a first functional circuit. The first functional circuit exchanges signals and data with the DUT in an actual operating environment of the DUT, and performs a first test on the DUT using a first test signal. The first test signal is identical to a signal to be transmitted in the actual operating environment. The second board includes a processor and a multiplexer. The processor performs a second test different from the first test on the DUT using a second test signal. The second test signal is different from the first test signal and checks an electrical characteristic of the DUT itself. The multiplexer selects one of the first test signal and the second test signal to transmit to the DUT.

The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.

A structure for signal transmission is disclosed. The structure comprises a first plurality of waveguides tightly disposed together and disposed substantially in parallel with each other, each of said waveguides having a first opening and a second opening, wherein each first opening is operable to align with a patch antenna, and wherein the first plurality of waveguides is disposed adjacent to a socket. The integrated structure further comprises the socket which comprises an opening operable to support an insertion of a device under test (DUT), wherein the DUT is communicatively coupled to a plurality of microstrip transmission lines on a printed circuit board (PCB) underlying the socket for transmitting test signals from the DUT, wherein each of the microstrip transmission lines is electrically coupled to a respective patch antenna. Further, the first plurality of waveguides and the socket are integrated into a single plastic or metal structure.

Embodiments of the present disclosure use customizable waveguides that can be positioned next to each other in a structure that contains one single flange to provide a physical connection for the waveguides. In this fashion, many waveguides can be positioned within a small area to accommodate a tightly packed patch antenna array so that the waveguides can be positioned very close to the socket. As such, embodiments of the present disclosure allow more waveguides to be packed into a small area by providing a single structure that houses many waveguides and share only a single flange connection element that can be sized appropriately.

Systems and techniques for obtaining and maintaining maintenance records for various assets are described. In one embodiment, a computing device may be wirelessly coupled to a measurement device when the computing device is placed in proximity with the computing device. Upon measuring one or more parameters of a device under test (DUT), the measurement device may provide the measured parameters to the computing device in the form of measurement data. In some embodiments, the computing device associates the measured parameters with the corresponding DUT from which the measurements were obtained and provides the associated measured parameter to, for example, a service provider for future access. In another embodiment, the measurement device itself is configured to associate the measurement parameters with the DUT and provide the associated measurement parameters to the service provider.

A system and method for testing electronic circuit devices. The system has a central processing unit with a plurality of separate core processing units. The utility service program is initiated at the startup of the computer program which acts as an intermediary between user applications and the computer operating system. The utility service is responsive to an ATE execution engine to set an affinity for one or more processing cores for exclusive use for the ATE execution engine. The ATE execution engine communicates with the utility service to reserve one or more processing cores for execution of the program for testing electronic devices.