Electric power Fault detection, isolation and restoration (FDIR) systems using smart switches that autonomously coordinate operations to minimize the number of customers affected by outages and their durations, without relying on communications with a central controller or between the smart switch points. The smart switches typically operate during the substation breaker reclose cycles while the substation breakers are open, which enables the substation breakers to reclose successfully to restore service within their normal reclosing cycles. Alternatively, the smart switch may be timed to operate before the substation breakers trip to effectively remove the substation breakers from the fault isolation process. Both approaches allow the FDIR system to be installed with minimal reconfiguration of the substation protection scheme.

A method, comprises: receiving measured air pressure data from each air data probe on a vehicle; receiving a first set of data from at least one sensor system on the vehicle; determining predicted noise levels for each air data probe using a noise modelling system and the received first set of data; determining a transmission loss for each air data probe; determining if any air data probe is faulty by determining if an transmission loss of any of the air data probes is greater than a first threshold value, where an air data probe is deemed faulty if its transmission loss is greater than the first threshold value; and if the transmission loss of any of the air data probes is greater than the first threshold value, then generating a signal to indicated that at least one air data probe is faulty.

A crack detection chip includes a chip which includes an internal region and an external region surrounding the internal region, a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region, an edge wiring disposed along an edge of the internal region in the form of a closed curve and a pad which is exposed on a surface of the chip and is connected to the edge wiring. The edge wiring is connected to a Time Domain Reflectometry (TDR) module which applies an incident wave to the edge wiring through the pad, and detects a reflected wave formed in the edge wiring to detect a position of a crack.

A semiconductor device includes a wiring substrate including a first surface and a second surface opposite to the first surface, a semiconductor chip including a plurality of chip electrodes and mounted over the wiring substrate, a first capacitor arranged at a position overlapping with the semiconductor chip in plan view and incorporated in the wiring substrate, and a second capacitor arranged between the first capacitor and a peripheral portion of the wiring substrate in plan view. Also, the second capacitor is inserted in series connection into a signal transmission path through which an electric signal is input to or output from the semiconductor chip.

A semiconductor device includes a semiconductor die, a detection structure, a path control circuit and a detection circuit. The semiconductor die includes a central region in which a semiconductor integrated circuit is provided and an external region surrounding the central region. The detection structure is provided in the external region. The path control circuit includes a plurality of switches that controls electrical connection of the detection structure. The detection circuit determines whether a defect is present in the semiconductor die and a location of the defect based on a difference signal. The difference signal corresponds to a difference between a forward direction test output signal and a backward direction test output signal obtained by propagating a test input signal through the detection structure in a forward direction and a backward direction, respectively, via the path control circuit.

Apparatus and associated methods relate to a functional self-test, including (1) generation of an excitation signal, (2) applying the excitation signal to a unit under test (UUT), the excitation signal including a cyclical signal for a first interval and substantially zero signal for a second interval, (3) determining frequency content of a UUT response signal, and (4) generating a fail result in response to the frequency content below a predetermined threshold. In an illustrative example, the UUT may be a piezoelectric element (PE). The UUT response signal may be processed by a filter, for example. A portion of the filtered UUT response signal, responding to the second interval of the excitation signal, may be analyzed by a fast Fourier transform module (FFTm), for example. In various implementations, the functional self-test may advantageously determine the health of a piezoelectric gas sensing element, periodically, in a field-deployed implementation.

There are provided a detection method and detection apparatus of an operating state of a circuit. The method includes: forming a neural network that acquires a state category of a circuit to be detected; measuring electrical characteristic parameters of at least one node in the circuit to be detected; inputting the measured electrical characteristic parameters of at least one node to the neural network, and obtaining the state category of the circuit to be detected through the neural network.

A non-linearity evaluation circuit for use with a signal generator having at least partly non-linear operation, the non-linearity evaluation circuit comprising: a detection unit operable to detect a given amplitude attribute in a target signal generated by the signal generator, the time position of the amplitude attribute in the target signal defining the time location of a snapshot time window relative to the target signal, the part of the target signal occupying the snapshot time window being a corresponding signal snapshot, and the presence of the given amplitude attribute indicating that the signal snapshot includes noise due to the non-linear operation of the signal generator; and a controller operable to analyse the signal snapshot rather than a larger part of the target signal and to evaluate the non-linear characteristics of the operation of the signal generator based on the analysis.

A light emitting element driving semiconductor integrated circuit constitutes at least a part of a light emitting element driving device arranged to drive a series connection unit including a plurality of light emitting elements. The light emitting element driving semiconductor integrated circuit includes a single-element short-circuit detection unit arranged to detect that one of the plurality of light emitting elements is short-circuited, and a control unit arranged to control a power element of the light emitting element driving device so that current supplied from the light emitting element driving device to the series connection unit is increased, when the single-element short-circuit detection circuit detects that one of the plurality of light emitting elements is short-circuited.

The present invention concerns a method and device for monitoring the gate signal of a power semiconductor (SI), the gate signal of the power semiconductor (SI) being provided by a gate driver (12), generates an expected signal (VGexp) that corresponds to the signal outputted by the gate driver (12) when no deterioration of the gate driver (12) and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists, compares the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (12), determines if a deterioration of the gate driver (12) and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists using the result of the comparing of the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (12).