An apparatus for detecting an operating characteristic mismatch at an output of an amplifier by using a replica circuit is presented. In one exemplary case, a detected voltage difference at the output of the two circuits is used to drive a tuning control loop to minimize an impedance mismatch at the output of the amplifier. In another exemplary case, the replica circuit is used to detect a fault in operation in a corresponding main circuit. A method for detecting a load mismatch in a main RF circuit using the replica circuit is also presented.

A deposition apparatus includes: a reaction chamber; a radio frequency (RF) power supply device configured to provide RF power to the reaction chamber; an RF sensing device configured to sense the RF power at each sub-unit time of each of multiple unit times; a computing device configured to compute an average value of intensities of the RF power measured at each sub-unit time of each of the unit times; and a fault detection and classification (FDC) device configured to: determine an occurrence of an arc based on the calculated average value of the intensities of the RF power; and generate a command signal based on the occurrence of the arc to control a reaction process.

A chip testing method includes the following operations: during a chip probe testing, executing, by a processor circuit in a chip, a code to generate a first test signal; and during the chip probe testing, utilizing the first test signal to perform a transition delay fault test on a first circuit in the chip.

Described embodiments include a fault monitoring system comprising a fault logic circuit having a fault logic input adaptable to be coupled to sensor inputs, and first and second fault logic outputs. The fault logic circuit compares a plurality of data values provided by respective sensor inputs to respective fault thresholds, and provides respective fault signals at the first fault logic output responsive to a fault event in which a respective data value exceeds its respective fault threshold. A timer has a timer input coupled to the reset output, and a timer output. A data register has a first data register input coupled to the write control output, a second data register input coupled to the timer output, and a data register output. The data register receives fault data that includes an event identifier, a timer value, and a timer expiration indicator.

A semiconductor device includes a first crack detection circuit configured to receive a first external detection signal and output the first external detection signal as a first internal detection signal through a first metal line or configured to receive the first internal detection signal through the first metal line and output the first internal detection signal as the first external detection signal, and a second crack detection circuit configured to receive the first internal detection signal and output the first internal detection signal as a second internal detection signal through a second metal line or configured to receive the second internal detection signal through the second metal line and output the second internal detection signal as the first internal detection signal.

A system for estimating faulted area in an electric distribution system. The system includes a database storing input data, a fault detection module to estimate, based on the input data, if a new faulted area estimation process is required, a condition estimation module to estimate condition of metered protective devices, un-metered protective devices, and metered devices (PMDs), an upstream to downstream module to assess condition of each metered protective device, un-metered protective device, and metered device (PMD), starting from a feeder circuit breaker towards feeder downstream, to estimate a tripped protective device and a last metered device upstream of a fault, and a downstream to upstream module configured to assess outaged electric loads or elements towards network upstream to find the common interrupting protective device.

A positive temperature coefficient (PTC) heater apparatus is provided and includes a PTC heater and a health monitoring unit. The PTC heater includes resistive elements arranged in balanced groups of a bridge formation. Each of the balanced groups is arranged in a corresponding one of the arms of the bridge formation. The health monitoring unit is electrically connected to the resistive elements. The health monitoring unit is configured to determine a fault condition of the PTC heater based on a fractional change of resistance of the bridge formation caused by a failure of any one or more of the resistive elements in any of the balanced groups of the arms of the bridge formation.

Disclosed herein are techniques related to detecting failures in piezo audio transducers. In some embodiments, the techniques may involve disabling non-essential components and peripherals and forcing microcontroller units into full active mode. The piezo audio transducer is driven at each of a plurality of driving frequencies and, for each driving frequency, the amount of power consumed by the piezo audio transducer is determined. Slope values are determined for each pair or driving frequencies. Based on these slopes, the disclosed techniques generate a piezo health metric for the piezo audio transducer indicating whether the piezo audio transducer passed or failed the test. If the piezo audio transducer fails the test, an appropriate warning or alert can be sent to one or more users and/or other devices.

A semiconductor device includes a semiconductor die, a detection structure, a path control circuit and a detection circuit. The semiconductor die includes a central region in which a semiconductor integrated circuit is provided and an external region surrounding the central region. The detection structure is provided in the external region. The path control circuit includes a plurality of switches that controls electrical connection of the detection structure. The detection circuit determines whether a defect is present in the semiconductor die and a location of the defect based on a difference signal. The difference signal corresponds to a difference between a forward direction test output signal and a backward direction test output signal obtained by propagating a test input signal through the detection structure in a forward direction and a backward direction, respectively, via the path control circuit.

According to an embodiment, a method for debugging a low-power domain in a multi-power domain device is disclosed. The method includes mapping a critical signal of the low-power domain to a latch circuit of a register bank; capturing, by the latch circuit, transitions of the critical signal in registers of the register bank; observing, by a core circuit in a switchable power domain of the multi-power domain device, registers of the register bank; and determining a fault corresponding to the critical signal based on a value of the registers of the register bank.