A gate driver circuit is provided that includes a high-side power transistor; a low-side power transistor coupled to the high-side power transistor, where an output voltage is generated at a load node coupled between the low-side power transistor and the high-side power transistor; a gate driver configured to receive a high-side control signal and a low-side control signal, drive the high-side power transistor based on the high-side control signal, and drive the low-side power transistor based on the low-side control signal; and a short circuit detection circuit configured to monitor for short circuit events at the high-side power transistor and at the low-side power transistor based on the high-side control signal, the low-side control signal, and the output voltage, and, generate a fault signal in response to detecting a short circuit event at either of the high-side power transistor or the low-side power transistor.

We disclose a circuit board that hosts at least first and second types of resistance sensors and a method of operating the same. The resistance of each sensor of the first type tends to increase, and the resistance of each sensor of the second type tends to decrease if the sensor is exposed to an aggressive environment. The circuit board also hosts a control circuit that operates to monitor respective resistances of the various resistance sensors and to process the digital values representing the resistances to estimate the working condition of one or more other electrical circuits located on the circuit board and/or in relatively close proximity to the circuit board in the corresponding equipment cabinet. The control circuit further operates to transmit out an appropriate alarm message if the estimated working condition is deemed unsatisfactory.

A load estimating device measures a voltage and a current supplied to a load connected with a generator, calculates a feature amount of the load, senses a remaining amount of fuel, outputs a time during which the load is continuously operable. The device estimates what the load connected with the generator is, based on the calculated feature amount and the feature amounts stored in a storage, and determines the time during which the estimated load is continuously operable, based on a power consumption of the estimated load, and the remaining amount of fuel. The device has a load registration mode for causing the storage to store therein a feature amount of a new load that is not stored in a storage.

Accordingly, an improved interposer connection testing technique is provided, employing parallel pseudo-random bit sequence (PRBS) generators to test all the interconnects in parallel and simultaneously detect any correctable defects. In one embodiment, a microelectronic assembly includes an interposer electrically connected in a flip-chip configuration to an originating IC (integrated circuit) die and to a destination IC die, the substrate having multiple conductive traces for a parallel communications bus between the IC dies. The originating IC die has a first parallel PRBS (pseudo-random binary sequence) generator to drive test PRBSs with different phases in parallel across the interposer traces. The destination IC die has a second parallel PRBS generator to create reference PRBSs with different phases, and a bitwise comparator coupled to receive the test PRBSs from the interposer traces and to compare them to the reference PRBSs to provide concurrent fault monitoring for each of the traces.

A circuit board testing device electrically coupled to a measurement gauge tests a circuit board. The circuit board testing device includes a processor configured to configure measurement parameters of the measurement gauge, configure measurement rules for testing the circuit board, confirm a circuit of the circuit board to be tested according to the record of test data, control the measurement gauge to test the circuit of the circuit board to be tested when the measurement gauge is electrically coupled to the circuit of the circuit board to be tested, receive measurement data returned by the measurement gauge, and analyze a faulty region of the circuit board according to the record of test data and the measurement data.

A circuit for detecting failure of a device includes a plurality of monitoring modules. Each respective monitoring module of the plurality of monitoring modules is configured to generate a monitoring value at an output of the respective monitoring module based on a signal received at an input of the respective monitoring module. The circuit further includes a data selector module configured to couple, for each step of a switching cycle, the input of each of the plurality of monitoring modules to one of a plurality of function modules such that each of the plurality of monitoring modules generates the monitoring value for each of the plurality of function modules to generate monitoring information and evaluation logic configured to determine whether a failure has occurred at the plurality of function modules based on the monitoring information.

The present disclosure pertains to systems and methods for detecting faults in an electric power delivery system. In one embodiment, system may include a data acquisition subsystem configured to receive a plurality of representations of electrical conditions. The system may also include an incremental quantities subsystem configured to calculate an incremental current quantity and an incremental voltage quantity based on the plurality of representations. A fault detection subsystem may be configured to determine a fault type based on the incremental current quantity and the incremental voltage quantity, to select an applicable loop quantity, and to declare a fault based on the applicable loop quantity, the incremental voltage quantity, and the incremental current quantity. A protective action subsystem may implement a protective action based on the declaration of the fault.

A temperature-managed equipment enclosure, wherein the fans are configured to draw air from the environment, and wherein damage sensors are distributed in a non-uniform and/or targeted manner. In an example embodiment, most of the damage sensors may be placed within a relatively narrow zone downstream from the cooling fans. In some embodiments, a relatively large percentage of the damage sensors may be placed in the areas characterized by one or more of the following: (i) relatively high linear velocity of the airflow; (ii) turbulent airflow; and (iii) a certain range of angles of impingement of airflow on the equipment surfaces. Advantageously, the disclosed placement of damage sensors can be used to enhance the ability to detect environmentally induced equipment damage with high sensitivity and/or certainty.

An ophthalmic device includes an enclosure that is compatible for wearing in or on an eye. An adjustable lens is disposed within the enclosure. Driver circuitry is disposed within the enclosure and coupled to drive the adjustable lens and change its optical power. Built-in-self-test (BIST) circuitry is disposed within the enclosure and coupled to the adjustable lens. The BIST circuitry includes an impedance measurement circuit coupled to selectively measure an impedance of the adjustable lens. A controller is disposed within the enclosure and includes BIST control logic that measures the impedance of the adjustable lens with the impedance measurement circuit to determine a health status of the adjustable lens.

A crack detection chip includes a chip which includes an internal region and an external region surrounding the internal region, a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region, an edge wiring disposed along an edge of the internal region in the form of a closed curve and a pad which is exposed on a surface of the chip and is connected to the edge wiring. The edge wiring is connected to a Time Domain Reflectometry (TDR) module which applies an incident wave to the edge wiring through the pad, and detects a reflected wave formed in the edge wiring to detect a position of a crack.