A method for detecting a physical short-circuit defect between the first metal layer and a gate below. A first detection structure and a second detection structure are arranged in parallel in a detection region or a dicing channel region on a wafer, each detection structure comprises a P-type active detection, a detection gate structure, a contact hole in the P-type active detection, gate contact holes at two ends of the detection gate structure, a metal wire connected to the contact hole in the P-type active detection, and a metal wire connected to the gate contact hole. The detection gate structure of the first detection structure and the metal wire above it at least partially overlap. However, there is no projective overlap region between the detection gate structure of the second detection structure and the metal wire—above it.

An apparatus for automatic testing of an electronic device includes a pad interface unit and measurement circuitry. The pad interface unit is configured to connect to pads of the electronic device. The measurement circuitry is configured to select a circuit path in the electronic device that passes via a digital signal pad from among the pads, which is configured to carry a digital signal, to estimate a non-binary measure indicative of an electrical resistance of the circuit path, by performing current-voltage measurements using the pad interface unit, and to determine, based on the non-binary measure, whether the digital signal pad passes or fails a test.

Electrical current flow in a ball grid array (BGA) package can be measured by an apparatus including an integrated circuit (IC) electrically connected to the BGA package. Solder balls connect the BGA package to a printed circuit board (PCB). A current sense loop can be fabricated on a wiring plane of the PCB to encircle a current supply via that supplies current to an IC mounted on the BGA package. A MUX/Sequencer can sequentially connect wires of the current sense loop to an amplifier. The amplifier can amplify a voltage induced on the current sense mesh by current flow into the BGA package. A sensing analog-to-digital converter (ADC) is electrically connected to convert a voltage at the output of the amplifier into digital output signals.

Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit incudes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

Provided is an integrated circuit and a test method for an integrated circuit. The integrated circuit includes at least one first branch and at least one second branch. The first branch includes at least one first capacitor. The first end of the first branch is electrically connected to the first end of the second branch, and the second end of the first branch is not connected to the second end of the second branch, to conduct a low-frequency test. The low-frequency test includes application of a low-frequency test signal between the first end of the first branch and the second end of the first branch to test the first branch.

The present application is applicable to the technical field of terahertz on-wafer measurement, and provides a new on-wafer S-parameter calibration method and device. The method includes: performing two-port calibration on a waveguide end face when a probe is not connected to a test system; performing one-port calibration on each of two probe end faces when the probe is connected to the test system; and fabricating a crosstalk calibration standard equal to a device under test in length on a substrate of the device under test, and correct a crosstalk error of the test system according to the crosstalk calibration standard. The present application can realize accurate characterization and correction of crosstalk error in a high-frequency on-wafer S-parameter calibration process, and improve the accuracy of error correction in high-frequency on-wafer S-parameter measurement.

A testing method and apparatus is disclosed for testing an integrated circuit device (100) which has a dedicated ground bias pad (121) connected across a high voltage electrostatic discharge clamp circuit (123) to a well-driving ground pad (122) by applying a first voltage to the dedicated ground bias pad to bias a wafer substrate (101) while simultaneously applying a second voltage to the well-driving ground pad to bias the well region (103), where the first and second voltage create a stressing voltage across a buried insulator layer (102, 105) in the integrated circuit device so that a screening test can be conducted to screen for a defect (106) in the buried insulator layer by measuring a leakage current.

Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

Embodiments of the invention include a computer-implemented method that includes controlling, using a processor, a high-resolution optical inspection tool (HROIT) to identify a reference die tamper circuit on a reference die of a wafer; and controlling, using the processor, a low-resolution optical inspection tool (LROIT) to use the reference die tamper circuit to determine that the reference die tamper circuit is on a second die of the wafer.

A test circuit includes an oscillator configured to generate an oscillation signal, a device-under-test (DUT) configured to output an AC signal based on the oscillation signal, a first detection circuit configured to generate a first DC voltage having a first value based on the oscillation signal, and a second detection circuit configured to generate a second DC voltage having a second value based on the AC signal.