A massively parallel wafer-level reliability system to test a reliability of wafers includes: a test platform; stations disposed on the test platform, wherein an individual test station receives a wafer and includes: a chuck disposed on the test platform; a probe including contactors that electrically contact the wafer; and a temperature controller to control a temperature of the wafer; a control platform disposed among the test stations; and a system controller to independently control the test stations and that is in electrical communication with the temperature controller, wherein the reliability of the wafers is tested in parallel by the test stations.

A method of testing an integrated circuit of a device is described. Air is allowed through a fluid line to modify a size of a volume defined between the first and second components of an actuator to move a contactor support structure relative to the apparatus and urge terminals on the contactor support structure against contacts on the device. Air is automatically released from the fluid line through a pressure relief valve when a pressure of the air in the fluid line reaches a predetermined value. The holder is moved relative to the apparatus frame to disengage the terminals from the contacts while maintaining the first and second components of the actuator in a substantially stationary relationship with one another. A connecting arrangement is provided including first and second connecting pieces with complementary interengaging formations that restricts movement of the contactor substrate relative to the distribution board substrate in a tangential direction.

An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.

The present disclosure provides a system and method enabling a self-burn-in test for a power supply device (PSD) of a server system using a multi-phase scheme. The PSD comprises a power-width modulation (PWM) controller, and a plurality of power stages. Each of the plurality of power stages comprises a driver, a high-side MOSFET, and a low-side MOSFET. In one aspect of the present disclosure, upon receiving a test mode command from a controller of the server system, the PWM controller can send a PWM signal to switch a specific power stage to the On state, and send at least another PWM signal that switches other power stage(s) of the plurality of power stages to the Tri-state. During a subsequent self-burn-in test of the specific power stage, low-side MOSFET(s) of the other power stage(s) can function as a load for the specific power stage.

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

A signal generation unit outputs a first AC signal and a second AC signal having different phases as noise. A first coaxial cable transmits a first AC signal. A second coaxial cable transmits a second AC signal. A first probe is connected to the first coaxial cable and arranged in proximity to an IC on a printed circuit board to apply the first AC signal to the IC. A second probe is connected to the second coaxial cable and arranged in proximity to the IC to apply the second AC signal to the IC. A determination device determines whether the IC is malfunctioning, based on a state of the IC after application of the first AC signal and the second AC signal.

A method of manufacturing a semiconductor device is provided. The method includes forming a conductive probe plug on an exposed portion of a die pad of a semiconductor die by way of an electroless plating process. A top surface of the conductive probe plug extends above a top surface of a top passivation layer of the semiconductor die. A copper pillar is formed over the conductive probe plug by way of an electrolytic plating process. Outer sidewalls of the copper pillar surround the top surface of the conductive probe plug. A top surface of the copper pillar is plated with a solder plate material and reflowed to form a solder cap on the top of the copper pillar.

A semiconductor device manufacturing method includes forming a plurality of semiconductor chips on a main surface of a semiconductor wafer, electrically testing each of the semiconductor chips, dicing the semiconductor wafer into individual semiconductor chips and assembling each of the semiconductor chips into a package to be a semiconductor device, subjecting the packages to a burn-in test, determining whether each of the semiconductor chips requires the burn-in test to be performed, and generating a determination model for determining whether the semiconductor chips require the burn-in test to be performed.

The present disclosure provides a system and method enabling a self-burn-in test for a power supply device (PSD) of a server system using a multi-phase scheme. The PSD comprises a power-width modulation (PWM) controller, and a plurality of power stages. Each of the plurality of power stages comprises a driver, a high-side MOSFET, and a low-side MOSFET. In one aspect of the present disclosure, upon receiving a test mode command from a controller of the server system, the PWM controller can send a PWM signal to switch a specific power stage to the On state, and send at least another PWM signal that switches other power stage(s) of the plurality of power stages to the Tri-state. During a subsequent self-burn-in test of the specific power stage, low-side MOSFET(s) of the other power stage(s) can function as a load for the specific power stage.