A value representative of a dispersion of a propagation delay of assemblies of electronic components is determined. A component test structure includes stages of components and a logic circuit connected in a ring. Each stage includes two assemblies of similar components configured to conduct a signal. A test device is configured to obtain values of the component test structure and to perform operations on these values.

A sensor system can include a sensor having a charge storage device controllably connected to a voltage source under control of a signal under test; and a readout circuit coupled to the charge storage device to determine whether the pulse width of the signal under test has changed greater than a threshold amount according to a voltage at the charge storage device. In some cases, the determination of whether the pulse width of the signal under test has changed can include determining whether the voltage satisfies a condition with respect to a comparison voltage. In some cases, the determination of whether the pulse width of the signal under test has changed can be based on a propagation delay through a delay chain, where the propagation delay is dependent on the voltage.

A system and method for the predictive maintenance of electronic components that includes sensors at at least one position via which present values of system parameters, such as temperature and voltage, and a signal propagation time at the at least one position are determined, where values of the system parameters and the signal propagation time presently determined by the sensors are retrieved by a central monitoring unit, an individual valid limit value is determined for the signal propagation time at each of the at least one position via the central monitoring unit based on the presently determined values of the system parameters, and the presently determined signal propagation time at each of the at least one position is compared with the associated valid limit value, and a notification is sent to a superordinate level, if the signal propagation time exceeds the limit value to trigger replacement of the electronic component.

An integrated circuit is provided. The integrated circuit includes a plurality of skitter circuits and a multiplexer that provides the waveform to the plurality of skitter circuits. The plurality of skitter circuits includes at least a first skitter circuit and a second skitter circuit. The first and second skitter circuits are arranged in parallel with respect to an output of the multiplexer. The first skitter circuit can include a first data path and a plurality of first inverters on that first data path. Further, the second skitter circuit can include a second data path, a plurality of second inverters on the second data path, and a delay element connected in series with an input of an initial inverter of the plurality of the second inverters on the second data path.

Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.

Provided are methods and systems for testing time parameters of an adaptor and systems. The method includes the following. After a testing system is coupled with an adaptor, a clock signal is received from the adaptor, where the clock signal is indicative of the transmission time of the instruction. A first valid interrupt of the clock signal, a square wave corresponding to the first valid interrupt, and a next valid interrupt of the first valid interrupt are acquired. A first falling edge and a first rising edge of the first valid interrupt, a second falling edge of the square wave, and a third falling edge of the next valid interrupt are acquired. A test result time parameters of the adaptor is generated according to the first falling edge, the first rising edge, the second falling edge, and the third falling edge.

A method for testing a semiconductor die is provided. The method includes the following steps: charging a die pad of the semiconductor die to a precharge level; stopping charging the die pad to detect a period of time required for a voltage level of the die pad to change from the precharge level to a reference level, and accordingly generating a detection result; and determining a leakage current of the die pad according to the detection result.

Disclosed are techniques that can be used in a semiconductor chip to determine performance such as timing performance. Among other features, supply voltages and clock rates may be adjusted to accommodate the operating temperature and to compensate for the processing variations that occurred when that chip was produced, or may occur as the chip is used. The techniques include determining a series of variables that affect performance, determining the sensitivity of timing paths in the circuit to each variable, duplicating the most sensitive paths. A novel sensor circuit is produced that includes the sensitive paths, which can be used to determine when the chip is performing as required and when it is not, and adjusting one or more supply voltages and/or clock rates in a static or real time manner when the circuit is not performing as required.

An integrated circuit (IC) includes a clocking system that generates first and second clock signals and a clock enable signal, and a testing system that tests the clocking system. During a capture phase of an at-speed testing mode of the IC, the second clock signal is a gated version of the first clock signal and includes two clock pulses. The testing system determines a first count of clock pulses of the first clock signal between an activation of the capture phase and an assertion of the clock enable signal. Similarly, the testing system determines a second count of clock pulses of the first clock signal between the two clock pulses of the second clock signal. The testing system then compares the first count with a first reference value and the second count with a second reference value to detect a fault in the clocking system.

Screening a batch of integrated circuits (IC) may be done with test patterns provided in a sequence of test vectors. The sequence of test vectors may be fetched from a memory coupled to a tester and then one or more bits from each test vector may be provided to the tester. A test pattern is formed by updating a latch in a periodic manner with a bit value from a same bit position from each of the sequence of test vectors. The test pattern may then be applied to an input pin of a device under test and a resulting signal may be monitored on an output pin of each one of the batch of ICs. A slow speed ICs may be screened by treating each IC that passes both a fast pattern test and a slow speed pattern test as a failure, for example.