One example includes a testing method that includes connecting a capacitor having a first capacitance to an output terminal of an integrated circuit (IC). The method can also include generating pulse signal responsive to an enable signal provided at at least one input terminal of the IC and providing a drive signal to the output terminal to cause a linearly increasing voltage across the capacitor responsive to the pulse signal. The method can also include measuring a no-load delay. The method can also include measuring the linearly increasing voltage at the output terminal responsive to the drive signal. The method can also include determining a first capacitance charge time for the capacitor responsive to the linearly increasing voltage reaching a threshold and determining a second capacitance charge delay for a second capacitance based on the first capacitance charge time and the no-load delay.

A device of measuring a duty cycle includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The control circuit is coupled to the resistor-capacitor circuit, and configured to acquire an ON-time according to the first voltage, the second voltage and the third voltage. The ON-time is a time interval during which the reference signal is in the first state.

An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.

Various implementations described herein are related to a method for constructing integrated circuitry and identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry. The method may include generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths. The method may include simulating corner points for the timing table, building diagonal points for the timing table based on the simulated corner points, and building remaining points for the timing table based on the simulated corner points and the diagonal points.

A calibration board and a timing calibration method thereof are provided. The calibration board for calibrating signal delays of test channels in an automatic test equipment is pluggably disposed in the automatic test equipment and includes calibration groups, a first common node, and a switching module. Each calibration group includes a second common node and conductive pads electrically connecting to the second common node. Each conductive pad selectively and electrically connects to one test channel. The switching module electrically connects to the first common node and each second common node. When a first delay calibration procedure is performed, the connection between the first common node and each second common node is disabled. When a second delay calibration procedure is performed, the connection between the first common node and each second common node is built.

A delay measurement circuit includes a transporting path selector, first and second delay measurement devices, and a controller. The delay measurement circuit forms a plurality of transporting loops through two of a first reference transporting conductive wire, a second reference transporting conductive wire, and a tested transporting conductive wire according to a control signal. The first delay measurement device respectively measures part of the transporting loops to obtain a plurality first transporting delays. The second delay measurement device respectively measures part of the transporting loops to obtain a plurality second transporting delays. The controller generates the control signal, and obtains a transporting delay of the tested transporting conductive wire according to the first transporting delays and the second transporting delays.

A method of operating a data processing system to generate a jitter-injected signal from an input signal that is a function of time is disclosed. A time offset corresponding to a first time is generated according to a jitter specification that specifies the offset as a function of time. The jitter-injected signal at the first time is generated by evaluating the input signal at a time equal to a sum of the time offset and the first time. If the jitter specification only provides offsets at signal crossing times, interpolation is used to derive time offsets at non-signal crossing times.

A degradation detection circuit may include a degradation unit including multiple delay elements driven by a high voltage for degradation. The high voltage for degradation value may be higher than an operation voltage. The degradation unit may be configured to provide a first delayed signal after passing a test signal through the degradation unit, wherein the test signal retains a pulse for a preset time. The degradation detection circuit may include a reference unit including a plurality of delay elements driven by the operation voltage, and configured to provide a second delayed signal after passing the test signal through the reference unit, a delay setting unit configured to provide a third delayed signal by selectively adding delay elements with respect to the second delayed signal, and a delay checking logic configured to detect a delay of the test signal by comparing the first delayed signal and the third delayed signal.

A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

A chip testing method includes: a data receiving window corresponding to each chip to be tested is determined; a time adjustment parameter corresponding to each chip to be tested is determined according to the data receiving window corresponding to each chip to be tested and a data input window preset for a test machine is determined; an actual input time point corresponding to each chip to be tested is determined according to the time adjustment parameter corresponding to each chip to be tested; and data is inputted to each chip to be tested at the actual input time point corresponding to the each chip to be tested, to enable each chip to be tested to receive the data inputted by the test machine in the data receiving window corresponding to the each chip to be tested.