A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

In order to expedite testing (such as silicon chip testing), a test pattern that indicates a timing, order, and frequency (e.g., speed) of signals sent during the test may be divided into different portions. Also, a frequency at which each portion of the test pattern is to be run is determined. Each portion is run at a frequency that can be supported by only that portion. As a result, the slowest portion of the test pattern only limits the frequency at which its portion is run, while other portions are run at a faster frequency. This reduces a time taken to run the test pattern in a testing environment.

Disclosed is a fixture including: a base including a bearing surface for bearing a T-CON board, and a limit mechanism for limiting displacement of the T-CON board in a direction parallel to the bearing surface; and a probe assembly for jointing with an upgrading lead port of the T-CON board, wherein the probe assembly is installed on the base and has an adjustable relative position with the bearing surface in a direction perpendicular to the bearing surface. When in upgrading, the T-CON board is arranged on the bearing surface of the base firstly, the position of the T-CON board is fixed by the limit mechanism, and the probe assembly is aligned with the upgrading lead port of the T-CON board, and is adjusted and moved in the direction perpendicular to the bearing surface so as to joint with the upgraded lead port of the T-CON board.

A system and method of testing an integrated circuit provide a first clock signal to a first flip-flop with an output to a functional circuit, provide a second clock signal to a second flip-flop with an input from the functional circuit, wherein the second flip-flip has a minimum hold time, provide a test input to the first flip-flop, observe a signal propagation time through the functional circuit, determine the signal propagation time is less than the minimum hold time of the second flip-flop, and increasing a timing separation by adding a unit of delay to the first clock signal or subtracting a unit of delay from the second clock signal.

An integrated circuit (IC) includes a clocking system that generates first and second clock signals and a clock enable signal, and a testing system that tests the clocking system. During a capture phase of an at-speed testing mode of the IC, the second clock signal is a gated version of the first clock signal and includes two clock pulses. The testing system determines a first count of clock pulses of the first clock signal between an activation of the capture phase and an assertion of the clock enable signal. Similarly, the testing system determines a second count of clock pulses of the first clock signal between the two clock pulses of the second clock signal. The testing system then compares the first count with a first reference value and the second count with a second reference value to detect a fault in the clocking system.

A semiconductor inspection device capable of detecting an abnormality with high sensitivity in a failure analysis of a fine-structured device is provided. An electron optical system radiates an electron beam to a sample on a sample stage. A measurement device measures an output from a measurement probe that is in contact with the sample. An information processing device starts and stops the radiation of the electron beam to the sample, sets a first measurement period in which the measurement device measures the output from the measurement probe during the radiation and a second measurement period in which the measurement device measures the output from the measurement probe after the radiation, and obtains the measurement value of the output from the measurement probe based on a difference between a first measurement value measured in the first measurement period and a second measurement value measured in the second measurement period.

A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

A compensation circuit includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The resistor-capacitor circuit includes a first resistor-capacitor sub-circuit and a second resistor-capacitor sub-circuit. The first resistor-capacitor sub-circuit and the second resistor-capacitor sub-circuit are coupled to the control circuit, and operate simultaneously to compute an ON time of a front end module. The control circuit is coupled to the resistor-capacitor circuit, and is used to acquire the ON time according to the first voltage, the second voltage, and the third voltage, and includes an adjustment circuit used to generate a bias signal according to the ON time, and output the bias signal to the front end module.

A waveform data acquisition module includes an A/D converter that converts an electrical signal relating to a DUT into a digital signal, and a first memory unit that stores waveform data configured as a digital signal sequence. A function test module includes a test unit and a second memory unit. A higher-level controller instructs the waveform data acquisition module to start data sampling, and holds the time point thereof. Furthermore, the higher-level controller instructs the function test module to start to execute a pattern program, and records the time point thereof. The first memory unit records the time point at which the data sampling is started. The higher-level controller records the time point at which the execution of the pattern program is started.

A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.