Embodiments described herein provide an anisotropic conductive film (ACF) positioned on a semiconductor package and techniques of using the ACF to test semiconductor devices positioned in or on the semiconductor package. In one example, a semiconductor package comprises: a die stack comprising one or more dies; a molding compound encapsulating the die stack; a substrate on the molding compound; a contact pad on a surface of the substrate and coupled to the die stack; a test pad on the surface of the substrate; a conductive path between the contact pad and the test pad, where an electrical break is positioned along the conductive path; and an ACF over the electrical break. Compressing the ACF by a test pin creates an electrical path that replaces the electrical break. Data can be acquired by test pin and provided to a test apparatus, which determines whether the dies in the die stack are operating properly.

A memory temperature controlling method and a memory temperature controlling system are provided. The method includes: performing, by a testing equipment, test modes on a memory storage device, and obtaining a first internal temperature of a memory control circuit unit, a second internal temperature of each memory package and a surface temperature of each memory package to establish a linear relationship expression of the first internal temperature, the second internal temperature and the surface temperature; using, by the memory storage device, the linear relationship expression to calculate a predicted surface temperature of a rewritable non-volatile memory based on a first current internal temperature of the memory control circuit unit and a second current internal temperature of each memory package; adjusting, by the memory storage device, an operating frequency for accessing the rewritable non-volatile memory based on the predicted surface temperature.

Provided is an analyzing apparatus including a charge amount analyzing unit configured to analyze, by using a device simulator configured to simulate a transient change of a charge in a semiconductor device having a first main terminal and a second main terminal, a change of a charge amount at any one of the terminals when a power source voltage applied between the first main terminal and the second main terminal is changed by a displacement voltage smaller than an initial voltage after a current flowing between the first main terminal and the second main terminal is stabilized with the semiconductor device being set to an ON state and the power source voltage being set to the initial voltage, and a capacitance calculating unit configured to compute a terminal capacitance at any one of the terminals based on the change of the charge amount analyzed by the charge amount analyzing unit.

Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, a sub-pixel unit, a data line, a scan line, a plurality of test contact pads, a first peripheral-zone insulating layer and an auxiliary electrode layer. The base substrate includes a display zone and a peripheral zone, the peripheral zone including a test bonding zone. Each of the plurality of the test contact pads includes a first test-contact-pad metal layer and a second test-contact-pad metal layer, wherein the second test-contact-pad metal layer covers the first test-contact-pad metal layer and contacts the first test-contact-pad metal layer in at least portion of a periphery of the first test-contact-pad metal layer. The auxiliary electrode layer includes a plurality of first relay electrode patterns located within the test bonding zone and a plurality of auxiliary electrodes located within the display zone.

The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch, a second switch, and a third switch. The first switch has a first node coupled to a first device-under-test and a second node coupled to a first signal supply node. The second switch has a first node coupled to the second DUT and a second node coupled to the first signal supply node. The third switch has a first node directly coupled to the first DUT and the second DUT. The third switch has a second node coupled to a second signal supply node. The third switch selectively couples both of the first DUT and the second DUT to the second signal supply node.

Provided is a semiconductor device that allows reduction of a measurement time of a PCMTEG and improvement of productivity in an IC manufacturing process. A PCMTEG region 100 formed on a surface of a semiconductor substrate is divided into a main PCMTEG region 101 and a sub-PCMTEG region 102, and TEGs having specifications for their electrical characteristic values are all collectively arranged in the sub-PCMTEG region 102.

The present application provides a structure and method for online detection of a metal via open circuit, a contact layer is on the substrate, a first metal layer is on the contact layer, a first metal via layer is on the first metal layer, a second metal via layer is on the first metal via layer metal layer, the contact layer comprises a plurality of contacts, the plurality of contacts are connected to the first metal layer, the first metal via layer comprises a plurality of first vias, the plurality of first vias are filled with metal; detecting by means of an E-beam technology. A problem in the process can be found in advance, so as to solve the problem in time and thus stop losses as soon as possible.

A testing apparatus for Data Storage Devices (DSDs) includes a chassis and at least one interface module configured to be removably inserted into the chassis and house a plurality of interface boards. Each interface board includes a DSD connector for connecting a DSD to the interface board and a backplane connector for connecting to a backplane for communicating with a respective computing unit. In one aspect, the at least one interface module includes a housing and a plurality of openings in a side of the housing with each opening configured to receive a respective interface board. A plurality of guide member pairs is positioned to guide respective interface boards when inserted into respective openings such that the backplane connector is located at a respective predetermined location for connecting to the backplane. In another aspect, the interface boards are removable from the interface module.