A wafer inspection system and a wafer inspection equipment thereof are provided. The wafer inspection system includes a susceptor device, probe card, and bridge module. The susceptor device includes a susceptor unit for placing a wafer under test. The probe card includes a probing portion and conducting portion. The conducting portion is disposed at the periphery of the probing portion and has a contact surface. The bridge module includes transmission units extended upward, positioned adjacent to a wafer placement area, and coupled to the susceptor unit. When the probing portion comes into contact with a testing point of the wafer, the contact surface of the conducting portion gets coupled to the transmission units to transmit a test signal to the probe card via the transmission units and conducting portion and thus form a test loop. Thus, the test loop path can be shortened and the accuracy of signal transmission and inspection can be enhanced.

A test matrix adapter device having a plurality of segments arranged in a plane, the respective segments have line-shaped and column-shaped frame sections, and the segments are connected to one another in a form-fitting manner by the frame sections. Semiconductor receiving devices are arranged within the segments, that each have a plurality of first contact surfaces that are spaced apart from one another. The semiconductor receiving device are form-fittingly connected by webs to the frame sections of an assigned segment. The semiconductor receiving device has a bottom side and a base region at least partially enclosed by a frame, and an outer side. The column-shaped frame sections have projections that have second contact surfaces that are connected by conductor tracks to the first contact surfaces. The semiconductor receiving device adapted to receive a packaged semiconductor component with terminal contacts and to connect the terminal contacts to the first contact surfaces.

Embodiments of the present disclosure use customizable waveguides that can be positioned next to each other in a structure that contains one single flange to provide a physical connection for the waveguides. In this fashion, many waveguides can be positioned within a small area to accommodate a tightly packed patch antenna array so that the waveguides can be positioned very close to the socket. As such, embodiments of the present disclosure allow more waveguides to be packed into a small area by providing a single structure that houses many waveguides and share only a single flange connection element that can be sized appropriately.

Embodiments of the present disclosure utilize customizable waveguide fabrication technologies (e.g., 3D printer technology) and patch antenna arrays to create adaptable wave interfaces that can provide efficient signal routing for an ATE system. In this fashion, embodiments of the present disclosure allow for arbitrary waveguide routing from port to port and create high density port spacing at the PCB level and which specifically eliminates the large flange required of prior art waveguides. Furthermore, embodiments include the ability to integrate different waveguide components, including power splitters, couplers, terminations, etc., into a single structure. Thus, embodiments of the present disclosure can reduce signal path losses and simplify the mechanical construction of ATE systems while eliminating the need for coax cables and minimizing the length of PCB microstrips.

An integrated circuit that includes a processor also has an on-chip current test circuit that indirectly measures quiescent current in the processor. A supply voltage pin of the integrated circuit receives a supply voltage from an external test unit to provide power to the processor. The on-chip test circuit measures a voltage change across the processor during a predetermined test period T when the processor is isolated from the supply voltage and the clock signal is stopped. The voltage change provides an indication of quiescent current corresponding to the processor.

Provided are an inspection jig and an inspection apparatus in which a configuration for bending a plurality of contacts in the same direction can be simplified. The inspection jig includes a plurality of contacts each of which has a rod shape, a first support portion that supports the first end portion side of the plurality of contacts, and a second support portion that supports the second end portion side of the plurality of contacts. The first support portion includes a facing support plate that is disposed to face the second support portion in a manner separated from the second support portion and has a plurality of through holes through which the plurality of contacts are inserted, and a cross section of each of the through holes has an elliptical shape whose major axis extends in a predetermined specific direction along a plane direction of the facing support plate.

An apparatus for measuring a device current of a device under test (DUT) includes a first circuit including a first terminal for coupling to a first connection terminal of the DUT. The first circuit is configured to supply a first test voltage for the first terminal and to output a first output voltage sensed at the first terminal. The apparatus further includes a second circuit having a second terminal for coupling to a second connection terminal of the DUT. The second circuit is configured to supply a second test voltage for the second terminal and to output a second output voltage sensed at the second terminal. The apparatus further includes a third circuit configured to determine the device current of the DUT based on the first output voltage, the second output voltage, the first test voltage and the second test voltage. The first circuit and the second circuit are identical.

An electrical Kelvin contact assembly for testing IC testing apparatus that uses an assembly design that reduces the tolerance to a near negligible range. The assembly does not use any screws, dowel pins, adhesives or welding to fasten the electrical contacts to the housing. The design of the assembly uses rows of contacts with specially designed protrusions that sit snugly in openings located on three plate-like layers. These layers contain the contacts in the horizontal plane by securing the protrusions in the opening, as well as in the vertical plane by means of a sandwich between three separate layers. A second contact is slid into back slits formed by the three layers.

A nontransitory computer-readable program storage medium storing program instructions. The program, when executed by a processor, has the processor capable of receiving a set of input data, the input data relating to devices on a test board for testing a device under test. The program, when executed by a processor, also is capable of transforming the set of input data into test board mapping data. The test board mapping data comprises an ordered listing of potential test points along a path that couples to a conductive surface, wherein the potential test points are derived from at least one of the test board attributes. Further, the program, when executed by a processor, is capable of identifying a selected test point from among the one or more potential test points, the selected test point for spike check probing of the device under test.

An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.