A glitch detection circuit includes a first P-type field-effect transistor and a second P-type field-effect transistor which are biased by the same current, and a channel width-to-length ratio of the first P-type field-effect transistor is higher than that of the second P-type field-effect transistor. A capacitor having a terminal grounded and another terminal connected to the gates of the first and second P-type field-effect transistors and a power supply terminal. A determination circuit configured to determine that a negative glitch occurs when a voltage decreasing amount of the drain of the first P-type field-effect transistor is greater than that of the second P-type field-effect transistor, and determine that a positive glitch occurs when an voltage increasing amount of the drain of the second P-type field-effect transistor is greater than that of the first P-type field-effect transistor.

Provided is an integrated circuit and a test method for an integrated circuit. The integrated circuit includes at least one first branch and at least one second branch. The first branch includes at least one first capacitor. The first end of the first branch is electrically connected to the first end of the second branch, and the second end of the first branch is not connected to the second end of the second branch, to conduct a low-frequency test. The low-frequency test includes application of a low-frequency test signal between the first end of the first branch and the second end of the first branch to test the first branch.

A method for detecting an abnormal die includes providing a wafer, determining the surrounding dies in accordance with a position of a target die on the wafer, calculating a difference between a value of an electrical characteristic of each of the surrounding dies and a value of an electrical characteristic of the target die to obtain the electrical characteristic deviations, ranking the absolute values of the electrical characteristic deviations to generate a ranking result, and determining the characteristic-related dies from the surrounding dies in accordance with the ranking result, determining a target-related area in accordance with the position of the target die, determining the target-related die from the characteristic-related dies in accordance with the target-related area and determining whether the target die is qualified in accordance with the target-related die.

A system and method for identifying latent reliability defects (LRD) in semiconductor devices are configured to perform one or more stress tests with one or more stress test tools on at least some of a plurality of wafers received from one or more in-line sample analysis tools to determine a passing set of the plurality of wafers and a failing set of the plurality of wafers, perform a reliability hit-back analysis on at least some of the failing set of the plurality of wafers, analyze the reliability hit-back analysis to determine one or more geographic locations of one or more die fail chains caused by one or more latent reliability defects (LRD), and perform a geographic hit-back analysis on the one or more geographic locations of the one or more die fail chains caused by the LRD.

A semiconductor failure analysis device includes an analysis part that analyzes a failure place in a semiconductor device; a marking part that irradiates the semiconductor device with laser light; a device arrangement part in which a wafer chuck, which holds the semiconductor device and on which an alignment target is provided, moves relative to the analysis part and the marking part; and a control part that outputs commands. The control part moves the wafer chuck to a position at which the analysis part is capable of taking an image of the alignment target, then outputs an alignment command that causes the marking part to be aligned with the analysis part with the alignment target as a reference, and irradiates the semiconductor device with laser light in a state in which a positional relationship between the marking part and the analysis part is maintained.

A testing circuit includes a first circuit and a second circuit. The first circuit and second circuit have a first capacitor and a second capacitor. The first circuit is connected to a first transistor. The second circuit is connected to a second transistor. A first inductor has a first terminal connected to an input of the testing circuit and a second terminal connected to a source of the second transistor. A first diode has an anode connected to ground and a cathode connected to the second terminal of the first inductor. The second capacitor has a first terminal connected to a drain of the second transistor and a second terminal connected to ground. The first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground.

A test system includes: a test board on which a plurality of test target devices are mounted while being sequentially connected to one another; a measuring apparatus configured to simultaneously execute direct current tests for the test target devices mounted on the test board; and a determining apparatus configured to determine whether or not the test target devices are acceptable. The measuring apparatus executes the direct current tests every time when the number of test target devices mounted on the test board changes. The measuring apparatus determines whether or not the test target devices are acceptable on the basis of a change between measured values of the direct current tests, which follows the change of the number of test target devices mounted on the test board.

A method for detecting an abnormal die includes providing a wafer, determining the surrounding dies in accordance with a position of a target die on the wafer, calculating a difference between a value of an electrical characteristic of each of the surrounding dies and a value of an electrical characteristic of the target die to obtain the electrical characteristic deviations, ranking the absolute values of the electrical characteristic deviations to generate a ranking result, and determining the characteristic-related dies from the surrounding dies in accordance with the ranking result, determining a target-related area in accordance with the position of the target die, determining the target-related die from the characteristic-related dies in accordance with the target-related area and determining whether the target die is qualified in accordance with the target-related die.

A system and method for evaluating the reliability of semiconductor die packages are configured to sort a plurality of semiconductor dies with a Known Good Die (KGD) subsystem based on a comparison of an inline part average testing (I-PAT) score of each of the plurality of semiconductor dies to a plurality of I-PAT score thresholds, where the semiconductor die data includes the I-PAT score for each of the plurality of semiconductor dies, where the I-PAT score represents a weighted defectivity of the corresponding semiconductor die. The semiconductor dies may be filtered to remove at-risk semiconductor dies prior to sorting. The semiconductor die data may be received from a plurality of semiconductor die supplier subsystems. The KGD subsystem may transmit semiconductor die reliability data about the sorted plurality of semiconductor dies to a plurality of semiconductor die packager subsystems.

Provided are a sampling measurement method and system, computer device and storage medium. The sampling measurement method includes: acquiring a preset measurement ratio of each process element in a process station; acquiring an actual measurement ratio of a process element associated with a lot of products to be measured that arrive at the measurement station in the process station; and, when the actual measurement ratio of the associated process element is less than the corresponding preset measurement ratio, controlling a measurement machine at the measurement station to measure the lot of products to be measured.