An electronic device including a processor and a sensor may be provided. The processor obtains a first degree of degradation of a first core based on a first parameter value associated with a lifetime of the first core and a first operating level associated with an operation of the first core. The processor obtains a second degree of degradation of a second core based on a second parameter value associated with a lifetime of the second core and a second operating level associated with an operation of the second core. The processor schedules a task of the first core and the second core based on the first degree of degradation and the second degree of degradation. The sensor provides the first parameter value and the first operating level to the first core and the second parameter value and the second operating level to the second core.

An apparatus for determining a single decision function is configured to obtain measurements from a plurality of devices under test corresponding to stimulating signals applied to the plurality of devices under test. The stimulating signals correspond to a set of tests performed on the plurality of devices under test. The apparatus may further determine a subset of tests from the set of tests, such that the subset of tests is relevant for indicating whether the plurality of devices under test pass the set of tests. The apparatus may also determine the single decision function applicable to measurements from an additional device under test tested using the subset of tests, such that the single decision function is adapted to predict a test result for the set of tests on the basis of the subset of tests.

The method may be used for measuring an electric property of a magnetic tunnel junction used in an embedded MRAM memory for example. The method uses a multi point probe with a plurality of probe tips for contacting a designated area of the test sample, which is electrically insulated from the part of the test sample which is to be tested. Electrically connections are placed underneath the magnetic tunnel junction and goes to the designated area.

A multi-station concurrent testing method, comprising: a step A in which the control station controls the handler to send SOT signal(s) of corresponding testing station(s) based on previous testing results at adjacent testing stations of the testing stations; a step B in which the control station constructs an SOT signal sequence based on the received SOT signal(s) and in correspondence to orders of the testing stations; and a step C in which the control station compares the SOT signal sequence and an SOT signal prediction value sequence generated by the control station, wherein if the SOT signal sequence and the SOT signal prediction value sequence match, the corresponding testing station(s) executes the test of device(s) under test, and otherwise, the handler is controlled to purge the devices under test at the testing stations, the SOT signal prediction value sequence is generated based on previous testing results at the testing stations.

A glitch detection circuit includes a first P-type field-effect transistor and a second P-type field-effect transistor which are biased by the same current, and a channel width-to-length ratio of the first P-type field-effect transistor is higher than that of the second P-type field-effect transistor. A capacitor having a terminal grounded and another terminal connected to the gates of the first and second P-type field-effect transistors and a power supply terminal. A determination circuit configured to determine that a negative glitch occurs when a voltage decreasing amount of the drain of the first P-type field-effect transistor is greater than that of the second P-type field-effect transistor, and determine that a positive glitch occurs when an voltage increasing amount of the drain of the second P-type field-effect transistor is greater than that of the first P-type field-effect transistor.

A system and method for identifying latent reliability defects (LRD) in semiconductor devices are configured to perform one or more stress tests with one or more stress test tools on at least some of a plurality of wafers received from one or more in-line sample analysis tools to determine a passing set of the plurality of wafers and a failing set of the plurality of wafers, perform a reliability hit-back analysis on at least some of the failing set of the plurality of wafers, analyze the reliability hit-back analysis to determine one or more geographic locations of one or more die fail chains caused by one or more latent reliability defects (LRD), and perform a geographic hit-back analysis on the one or more geographic locations of the one or more die fail chains caused by the LRD.

A health monitoring, assessing and response system includes an interface and a controller. The interface is configured to receive a signal from a sensor disposed in a substrate processing system. The controller includes a health index module. The health index module is configured to perform an algorithm including: obtaining a window and a boundary threshold; monitoring the signal output from the sensor; determining whether the signal has crossed the boundary threshold; updating a health index component, where the health index component is a binary value and transitioned between HIGH and LOW values in response to the signal crossing the boundary threshold; and generating a health index value based on the health index component and decreasing the health index value from 100% to 0% over a duration of at least the window. The controller is configured to perform a countermeasure based on the health index value.

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

Systems and methods for determining location of critical dimension (CD) measurement or inspection are disclosed. Real-time selection of locations to take critical dimension measurements based on potential impact of critical dimension variations at the locations can be performed. The design of a semiconductor device also can be used to predict locations that may be impacted by critical dimension variations. Based on an ordered location list, which can include ranking or criticality, critical dimension can be measured at selected locations. Results can be used to refine a critical dimension location prediction model.

The present invention discloses an information management method and system for IC tests, and a storage medium. The method comprises steps of: providing test data generated by performing an IC test by an IC test platform, the IC test platform being an IC test platform having more than one stage, each stage of the IC test platform comprising a plurality of test devices: providing resource data related to the IC test, other than the test data; and analyzing the IC test according to the test data of the IC test and the resource data, to obtain result data related to the IC test. In this way, the present invention can provide technical support for utilizing the value of test data generated in IC tests.