The present disclosure discloses an assembly for carrying a chip, and a device and a method for testing a chip. The assembly for carrying a chip is configured to fasten chips of different sizes, and includes a rotatable vertical rod, a cross beam, a first sidewall, and a second sidewall. The rotatable vertical rod is provided with a gear that surrounds the rotatable vertical rod with gear teeth. The cross beam is internally provided with a first through hole and a first chute. A top of the first sidewall is connected to a first connecting rod located in the first chute. A top of the second sidewall is connected to a second connecting rod located in the first chute. A side surface of the first connecting rod is provided with a plurality of first tooth grooves arranged linearly.

A method comprising activating an internal switch within a packaged electronic device to connect to a reference ground of an internal voltage source to a first input of an analog front end, receiving an external ground potential voltage at a first package pin of the packaged electronic device, generating a zero detector output signal for the packaged electronic device at a second package pin, activating the internal switch to connect the first input of the analog front end to the internal voltage source, receiving a second voltage level at the first package pin that generates a second output signal that matches the zero detector output signal, and receiving trim instructions to trim an internal voltage generated by the internal voltage source to a voltage level that is closer to a target voltage level.

A manufacturing method of a semiconductor package includes the following steps. Semiconductor chips are disposed on a carrier. The semiconductor chips are grouped in a plurality of package units. The semiconductor chips are encapsulated in an encapsulant to form a reconstructed wafer. A redistribution structure is formed on the encapsulant. The redistribution structure electrically connects the semiconductor chips within a same package unit of the plurality of package units. The individual package units are separated by cutting through the reconstructed wafer along scribe line regions. In the reconstructed wafer, the plurality of package units are arranged so as to balance the number of scribe line regions extending across opposite halves of the reconstructed wafer in a first direction with respect to the number of scribe line regions extending across opposite halves of the reconstructed wafer in a second direction perpendicular to the first direction.

A testing equipment is provided, in which at least one testing module is disposed on a machine, and the testing module includes a circuit board, a testing carrier disposed on the circuit board and carrying a target object, and a processor disposed on the circuit board and electrically connected to the testing carrier, such that the testing module can operate and process a target information of the target object by itself via the processor, without connecting to an external computer to operate and process the target information of the target object, so as to quickly obtain a detecting information of the target object.

An illuminator system for semiconductor chip testing has a rotary plate and a first light source and second light source mounted on the rotary plate. A controller is configured to rotate the rotary plate to provide a desired light output. A light output of the illuminator system is aligned to the desired first or second light source. A first semiconductor chip receives illumination from the desired source. The rotary plate is rotated until the desired light source is aligned to the light output. A quality or characteristic of light emitted by the first light source can be measured, and then the first light source can be adjusted, or an alert can be generated, if the quality or characteristic falls outside of a preconfigured range.

Electrical current flow in a ball grid array (BGA) package can be measured by an apparatus including an integrated circuit (IC) electrically connected to the BGA package. Solder balls connect the BGA package to a printed circuit board (PCB) and are arranged to provide a contiguous channel for a current sense wire. A subset of solder balls is electrically connected to supply current from the PCB through the BGA package to the IC. The current sense wire is attached to the upper surface of the PCB, within the contiguous channel, and surrounds the subset of solder balls. An amplifier is electrically connected to the current sense wire ends to amplify a voltage induced on the current sense wire by current flow into the BGA package. A sensing analog-to-digital converter (ADC) is electrically connected to convert a voltage at the output of the amplifier into digital output signals.

A method for assessing a thermal path associated with an integrated circuit includes identifying a heat application mode based on a design type of the integrated circuit. The method also includes measuring a first temperature of at least one thermal sensing device associated with the integrated circuit. The method also includes applying heat to at least a portion of the integrated circuit according to the heat application mode. The method also includes measuring a second temperature of the at least one thermal sensing device. The method also includes determining a difference between the first temperature and the second temperature. The method also includes determining whether a thermal path between the integrated circuit and an associated substrate is sufficient based on a comparison of the difference between the first temperature and the second temperature with a predetermined difference between an initial temperature and a subsequent temperature of the at least one thermal sensing device.

Methods and apparatus of forming a thermal interface with condensate are described. In an example, a device may be disposed in a test environment or a test apparatus. An amount of condensate may be accumulated on a heat sink to coat the heat sink with a layer of condensate. The coated heat sink may be disposed on the device, where the layer of condensate is directed towards the device, and the disposal of the coated heat sink causes the layer of condensate to spread among voids between the heat sink and the device to form a thermal interface that includes the condensate. A test may be executed on the device with the thermal interface comprising the condensate between the coated heat sink and the device.

Examples disclosed herein relate to a on-chip or built-in self-test (BIST) module for an RFIC including means to up-convert a signal from a test frequency to RF at an input to the RFIC and down-convert and output signal.

A system includes a platform and a contactor. The platform has a side configured to support a frame with a carrier structure and electronic devices each having first and second sides and a terminal, the first side positioned on the carrier structure, and the terminal exposed in a first portion of the second side. The contactor has first and second sides, a contact and a heater. The contact is exposed on the first side of the contactor to contact the terminal in a first portion of the second side of a selected one of the electronic devices, and the heater is exposed on the first side of the contactor to apply heat to a second portion of the second side of the selected one of the electronic devices.