Patent classifications
G01R31/2898
HIGH POWER DEVICE FAULT LOCALIZATION VIA DIE SURFACE CONTOURING
A method of preparing a computer processor die includes determining a warpage shape of the computer processor die at a testing temperature. The method also includes selectively contouring a thickness of the computer processor die at a contouring temperature by physically removing material from a surface of the computer processor die such that the surface will be substantially flat at the testing temperature.
DIE EXTRACTION METHOD
Provided is a die extraction method, comprising the following steps: removing solder balls; polishing a front side of the sample to remove a part on a front side of the target die, and retain a part of a die attach film (DAF) layer on the front side of the target die and a bonding wire located in the part; attaching the front side of the sample to the polishing jig and flattening the sample and the polishing jig by the flattener; polishing the back side of the sample to remove a part on a back side of the target die, and retain a DAF layer on the back side of the target die; removing the DAF and a packaging material remaining on the sample to obtain the target die; and attaching the back side of the target die to a glass slide, thus completing extraction of the target die.
Assembly and method for performing in-situ endpoint detection when backside milling silicon based devices
An assembly for monitoring a semiconductor device under test comprising a mill configured to mill the device, a sensor configured to measure an electrical characteristic of the device, and a computer configured to determine the amount of strain in the device from the electrical characteristic when the mill is milling the device and detect an endpoint of milling at a circuit within the device. In use the endpoints of the milling process of the semiconductor device are detected measuring an electrical characteristic of the device with a sensor during milling determining the amount of strain in the device from the electrical characteristic and detecting an endpoint of the milling process within the device based on the amount of strain.
ION BEAM DELAYERING SYSTEM AND METHOD, TOPOGRAPHICALLY ENHANCED DELAYERED SAMPLE PRODUCED THEREBY, AND IMAGING METHODS AND SYSTEMS RELATED THERETO
Described are various embodiments of an ion beam delayering system and method, topographically enhanced sample produced thereby, and imaging methods and systems related thereto. In one embodiment, a method comprises: identifying at least two materials in an exposed surface of the sample and predetermined operational characteristics of an ion beam mill that correspond with a substantially different ion beam mill removal rate for at least one of the materials; operating the ion beam mill in accordance with the predetermined operational characteristics to simultaneously remove the materials and introduce or enhance a topography associated with the materials and surface features defined thereby; acquiring surface data; and repeating the operating and acquiring steps for at least one more layer.
METHODS AND STRUCTURES FOR SEMICONDUCTOR DEVICE TESTING
A structure for performing analysis includes a first opening formed on a back side of a substrate and passing through the substrate, a second opening connected with a bottom of the first opening and penetrating into a first dielectric layer formed on a front side of the substrate, a first conductive layer formed on a sidewall of the second opening and a contact element in the first dielectric layer, and a second conductive layer formed on a second dielectric layer. The first conductive layer contacts the second conductive layer electrically.
Method of preparing a semiconductor specimen for failure analysis
The present invention discloses a method for preparing a semiconductor sample for failure analysis, which is characterized by using an adhesive layer comprising a non-volatile and non-liquid adhesive material with higher adhesion to the dielectric materials and lower adhesion to the metallic contact materials to selectively remove part of the dielectric materials in a large area with high uniformity, but completely remain the metallic contact materials, and not chemically react with the semiconductor specimens or even damage to the structures of interest to be analyzed, and different adhesive materials can be selected as the adhesive layer to control the adhesion to the dielectric layer, thereby the removed thickness of the dielectric layer can be controlled to provide a semiconductor specimen for failure analysis.
Assembly and Method for Performing In-Situ Endpoint Detection When Backside Milling Silicon Based Devices
An assembly for monitoring a semiconductor device under test comprising a mill configured to mill the device, a sensor configured to measure an electrical characteristic of the device, and a computer configured to determine the amount of strain in the device from the electrical characteristic when the mill is milling the device and detect an endpoint of milling at a circuit within the device. In use the endpoints of the milling process of the semiconductor device are detected measuring an electrical characteristic of the device with a sensor during milling determining the amount of strain in the device from the electrical characteristic and detecting an endpoint of the milling process within the device based on the amount of strain.
Encapsulated component attachment technique using a UV-cure conductive adhesive
A method for acquiring a signal from an encapsulated test point on a device under test, includes forming a hole in an encapsulant adjacent to the test point, the hole extending through the encapsulant to the test point, delivering a UV-curable conductive adhesive into the hole such that the delivered adhesive contacts the test point, applying UV light from a UV light source to cure the delivered adhesive, and connecting a conductive element between the cured adhesive and a test and measurement instrument.
Method for delidding a hermetically sealed circuit package
A method of delidding an integrated circuit (IC) package includes directing a laser beam along a cut line of an integrated circuit package. The cut line defines a removable portion, the cutting occurs along the cut line, and the removable portion is removed after the directing. A method of troubleshooting an integrated circuit package is also disclosed.
System and method of preparing integrated circuits for backside probing using charged particle beams
Described herein are a system and method of preparing integrated circuits (ICs) so that the ICs remain electrically active and can have their active circuitry probed for diagnostic and characterization purposes using charged particle beams. The system employs an infrared camera capable of looking through the silicon substrate of the ICs to image electrical circuits therein, a focused ion beam system that can both image the IC and selectively remove substrate material from the IC, a scanning electron microscope that can both image structures on the IC and measure voltage contrast signals from active circuits on the IC, and a means of extracting heat generated by the active IC. The method uses the system to identify the region of the IC to be probed, and to selectively remove all substrate material over the region to be probed using ion bombardment, and further identifies endpoint detection means of milling to the required depth so as to observe electrical states and waveforms on the active IC.