G01R31/2898

Method of identifying vulnerable regions in an integrated circuit

A method of designing a robust integrated circuit that is not vulnerable to optical fault injection comprises training a variational autoencoder to identify regions in a target integrated circuit that are vulnerable to optical fault injection and altering the design of the target integrated circuit by altering the design of the vulnerable regions so that the target integrated circuit is no longer vulnerable to optical fault injection, thereby forming the robust integrated circuit.

REPACKAGING IC CHIP FOR FAULT IDENTIFICATION

A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Method of Identifying Vulnerable Regions in an Integrated Circuit
20250199061 · 2025-06-19 ·

A method of designing a robust integrated circuit that is not vulnerable to optical fault injection comprises training a variational autoencoder to identify regions in a target integrated circuit that are vulnerable to optical fault injection and altering the design of the target integrated circuit by altering the design of the vulnerable regions so that the target integrated circuit is no longer vulnerable to optical fault injection, thereby forming the robust integrated circuit.

Contrast-enhancing staining system and method and imaging methods and systems related thereto

Described are various embodiments of a contrast-enhancing staining system and method. In one embodiment, a method is described for enhancing contrast in an image of a substrate surface between regions of said substrate having different charge carrier characteristics. The method comprises exposing said substrate to a staining precursor comprising an oxidant; directing microwave electromagnetic radiation at the substrate, said microwave electromagnetic radiation enhancing a reaction rate of said oxidant reacting into a deposition material, said reaction rate being related to the charge carrier characteristics of a proximal region; and acquiring an image of said substrate surface indicating a visual contrast between each of said regions based on differential deposition of the deposition material therebetween.