Automatic voltage reconfiguration in a computer processor including one or more cores includes executing one or more user-specified workloads; determining, based on the user-specified workloads, a respective minimum safe voltage for each core of one or more cores; and modifying a respective voltage configuration for each core of the one or more cores based on the respective minimum safe voltage.

The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.

A voltage application device of a tester includes a voltage setting controller that sets a number of transient steps, step time, and step voltage as transient voltage setting parameters; and a device power supply (DPS) configured to supply power to the plurality of devices under test formed on a substrate. The voltage application device outputs an output voltage having a step-like transient voltage waveform based on the transient voltage setting parameters set by the voltage setting controller. The voltage application device is a high-order lag system of a second-order or higher in which an overshoot occurs in a response with respect to a set voltage. An end point of a step time of each of the transient steps set in the voltage setting controller is set to be a time between an end point of a rising time and an overshoot time.

A system and method for measuring power supply variations are described. A functional unit includes one or more power supply monitors capable of measuring power supply variations. The power supply monitors forego use of a clock signal from clock generating circuitry and forego use of a reference voltage from a reference power supply. The power supply monitors use an output of a source ring oscillator as a clock signal for the sequential elements of a counter. The counter measures a number of revolutions of a measuring ring oscillator within a period of the output of the source oscillator. The revolutions of the measuring ring oscillator are associated with a number of rising edges and falling edges of the output signal of the measuring ring oscillator. An encoder converts the output of the sequential elements to a binary value, and sends the binary value to an external age tracking unit.

A testing device includes a measuring unit, a testing board supporting the measuring unit and connected to the measuring unit, and a connecting interface coupled to the testing board. The connecting interface includes connecting terminals protruding in a direction away from the testing board, and is connected to a device under test (DUT) via the connecting terminals. When the DUT is connected to the connecting interface, the measuring unit supplies a constant electric current via the testing board and the connecting interface to the DUT for a preset duration to result in a voltage, measures the voltage, and determines, based on a result of measurement of the voltage, an electrical connection status of the DUT.

The present application discloses a method for characterizing a resistance state of a programmable element of an integrated circuit. The method includes the steps of setting a first programming voltage of a first polarity to program the programmable element of the integrated circuit, setting a first read voltage of the first polarity to the integrated circuit at a first temperature to obtain a first read current, and a first resistance is derived from the first read current, setting the first read voltage of the first polarity to the integrated circuit at a second temperature to obtain a second read current, the second temperature is at least 50° C. higher than the first temperature, and a second resistance is derived from the second read current, and comparing the first resistance and the second resistance to characterize the resistance state of the programmable element.

A chip testing circuit and a testing method thereof are provided. The chip testing circuit includes a parameter measurement circuit, a plurality of power supply circuits, a plurality of switch circuits, and a control circuit. The plurality of power supply circuits respectively provide power supply to a plurality of chips carried by a plurality of sockets. Each switch circuit is electrically connected between one socket and one power supply circuit. The control circuit is connected in parallel to a plurality of signal pins of the plurality of chips carried by the plurality of sockets, so that when the control circuit outputs test data, all the chips can simultaneously receive the test data. When executing a parametric test mode, the control circuit controls one of the switch circuits to be turned on and controls the parameter measurement circuit to perform an electrical performance test on the chips.

A test and measurement instrument including a voltage source configured to output a source voltage, a current sensor, and one or more processors. The one or more processors are configured to determine an estimation of a load of an unknown connected device under test based on the source voltage, the current sensor, and a voltage of the connected device under test without any prior knowledge of the connected device under test.

The present disclosure provides methods for testing and evaluating electrical parameters of electronic circuits. An exemplary method includes providing a device-under-test electrically coupled to a testing apparatus; and determining an optimum value of a first electrical parameter and an optimum value of a second parameter by testing the device-under-test according to a set of first electrical parameter values and a set of second electrical parameter values. The optimum value of the first electrical parameter and the optimum value of the second parameter are determined based on an electrical noise response of the device-under-test.

An isolated differential current shunt measurement probe for a test and measurement system having an isolation barrier between an input side and output side of the probe. The input side is configured to receive a voltage signal across a current shunt connected to a device under test and transmit the voltage signal across the isolation barrier. The output side is configured to receive the voltage signal across the isolation barrier and output the voltage signal to a test and measurement instrument.