Thermal reduction and voltage adjustment techniques for computing systems and processing devices are presented herein. In a first example, a method of operating a voltage control system for a processing device includes operating the processing device in a computing assembly at a selected performance level, the processing device supplied with at least one input voltage at a first voltage level. The method includes monitoring thermal information associated with the computing assembly, and when the thermal information indicates a temperature associated with the computing assembly exceeds a threshold temperature, adjusting the at least one input voltage level supplied to the processing device to a second voltage level lower than the first voltage level and continuing to operate the processing device at the selected performance level.

Power reduction and voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method includes receiving a voltage characterization service over a communication interface of the computing apparatus as transferred by a deployment platform remote from the computing apparatus. The method includes executing the voltage characterization service for a processing device of the computing apparatus to determine at least one input voltage for the processing device lower than a manufacturer specified operating voltage, the voltage characterization service comprising a functional test that exercises the processing device at iteratively adjusted voltages in context with associated system elements of the computing apparatus. During execution of the voltage characterization service, the method includes monitoring for operational failures of at least the processing device, and responsive to the operational failures, restarting the processing device using a recovery voltage higher than a current value of the iteratively adjusted voltages.

An apparatus for performing multiple tests on a device under test (DUT) are provided. The apparatus includes at least one non-transitory computer-readable medium having stored thereon computer-executable instructions and at least one processor coupled to the at least one non-transitory computer-readable medium. The computer-executable instructions are executable by the at least one processor and cause the apparatus to perform operations of inputting a plurality of test patterns to a test apparatus, performing each of the plurality of test patterns on the DUT without interruption, and obtaining a respective result for the DUT in response to each of the plurality of test patterns.

An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; and an electronic monitoring circuit (100) that has a variably operable reference circuit (150) responsive to an input register (155) and having an output, comparison circuitry (110) having plural outputs and having a first input coupled to the output of said variably operable reference circuit (150) and a set of second inputs each second input coupled to a respective one of said power grid points (30.i); and an output register (120) having at least two register bit cells (120.i) respectively fed by the plural outputs of said comparison circuitry (110.i). Other integrated circuits, and processes of testing and of manufacturing are also disclosed.

A circuit screening system includes a target circuit under test, a power circuit, and a clock generating circuit. The target circuit under test receives a first testing signal in a first period, and a second testing signal in a second period, and the first testing signal is different from the second testing signal. The power circuit provides a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage maintains at a first voltage level in the first period, is pulled up to a second voltage level and back to the first level after the first period, and maintains at the first voltage level in a second period after the first period. The clock generating circuit provides a clock signal to the target circuit under test, wherein the clock signal has different profiles in the first period and the second period.

In some examples, a method of operating a circuit may comprise performing a circuit function under normal conditions, performing the circuit function under aggravated conditions, predicting a potential future problem with the circuit function under the normal conditions based on an output of the circuit function under the aggravated conditions, and outputting a predictive alert based on predicting the potential future problem.

A system and method for measuring power supply variations are described. A functional unit includes one or more power supply monitors capable of measuring power supply variations. The power supply monitors forego use of a clock signal from clock generating circuitry and forego use of a reference voltage from a reference power supply. The power supply monitors use an output of a source ring oscillator as a clock signal for the sequential elements of a counter. The counter measures a number of revolutions of a measuring ring oscillator within a period of the output of the source oscillator. The revolutions of the measuring ring oscillator are associated with a number of rising edges and falling edges of the output signal of the measuring ring oscillator. An encoder converts the output of the sequential elements to a binary value, and sends the binary value to an external age tracking unit.

An integrated circuit device includes general purpose input/output (I/O) circuitry having a transmit level shifter circuit in a transmit I/O circuit and a receive level shifter circuit in a receive I/O circuit. The integrated circuit device also includes an I/O pad which couples an output of the transmit level shifter circuit to an input of the receive level shifter circuit, a counter circuit, an inverter circuit coupled between the receive level shifter circuit and the counter circuit, and a logic gate. The logic gate includes a first input coupled to an output of the inverter circuit, a second input coupled to a counter_done signal from the counter circuit, and an output coupled to provide a data_out signal to an input of the transmit level shifter circuit.

A semiconductor chip includes a semiconductor device connected between a first node to which a power supply voltage is applied and a second node to which a ground voltage is applied, a first ring oscillator connected to the first node through a first supply switch and the second node through a first ground switch and a second ring oscillator connected to the first node through a second supply switch and the second node through a second ground switch, wherein the first supply and ground switches are configured to operate in response to a first control signal, thereby operating the first ring oscillator, and the second supply and ground switches are configured to operate in response to a second control signal, thereby operating the second ring oscillator.

A negative voltage testing including a monitoring and triggering circuit coupled to a supply voltage rail of a device under test (DUT) and a switching circuit coupled to the monitoring and triggering circuit. The monitoring and triggering circuit is configured to cause the switching circuit to provide a first negative voltage to the supply voltage rail when a supply voltage on the supply voltage rail decays below a predetermined level during a first test of the DUT.