Patent classifications
G01R31/3004
Control Apparatus, Device, Method and Computer Program for Determining a Device-Specific Supply Voltage for a Semiconductor Device
Examples relate to control apparatus, a control device, a method and a computer program for determining a device-specific supply voltage for a semiconductor device, and to a corresponding semiconductor device and corresponding systems. The control apparatus is configured to obtain measurement data of measurement circuitry of the semiconductor device, the measurement data being related to a progress of aging of the semiconductor device. The control apparatus is configured to determine the device-specific supply voltage of the semiconductor device based on the measurement data. The control apparatus is configured to provide information on the device-specific supply voltage for a supply voltage control apparatus.
Method for the characterization and monitoring of integrated circuits
A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.
TEST CIRCUIT AND METHOD
A test circuit includes an oscillator configured to generate an oscillation signal, a device-under-test (DUT) configured to output an AC signal based on the oscillation signal, a first detection circuit configured to generate a first DC voltage having a first value based on the oscillation signal, and a second detection circuit configured to generate a second DC voltage having a second value based on the AC signal.
Abnormality detection method and abnormality detection apparatus
An abnormality detection method according to one aspect of the present disclosure is a method of detecting an abnormality in an AC signal to be input from an AC power supply. The method includes, where an ideal AC signal is represented as V.sub.0 sin ωt (V.sub.0: amplitude, co: angular frequency, t: time), calculating an arithmetic value including a value represented by sin.sup.2ωt+cos.sup.2ωt and determining that the AC signal is abnormal when the arithmetic value is out of a threshold range.
SYSTEMS AND METHODS FOR PLP CAPACITOR HEALTH CHECK
Various implementations described herein relate to systems and methods for determining abnormal leakage current of a capacitor by determining a number of recent leakage current values for the capacitor and determining a maximum upper limit, minimum upper limit, maximum lower limit, and minimum lower limit based on leakage current values different from the recent leakage current values. A present upper limit and a present lower limit are determined for the recent leakage current values. Abnormal leakage current is determined in response to determining that the present upper limit being greater than an upper threshold (determined based on the maximum upper limit and the minimum upper limit) or the present lower limit being less than a lower threshold (determined based on the maximum lower limit and the minimum lower limit).
SYSTEMS AND METHODS FOR GENERATING AND MEASURING ELECTRICAL SIGNALS
Disclosed is a system for generating and measuring electrical signals. The system comprises a digital-to-analog converter module configured to generate one or more analog signals based on a control signal, and one or more channels. Each channel comprises an output terminal configured to be electrically connected to an electrical device, and a buffer circuit. The buffer circuit is configured to receive an analog signal of the one or more analog signals and to provide to the output terminal a voltage based on the voltage of the received analog signal. The buffer circuit is further configured to be electrically connected to a current source and to allow current to flow between the current source and the output terminal. The system further comprises a voltage measurement system and a current measurement system. The voltage measurement system is configured to measure, for each channel, a voltage indicative of the voltage at the output terminal of the channel. The current measurement system is configured to measure, for each channel, the current flowing through the output terminal of the channel. Also disclosed is method for generating and measuring electrical signals.
BUILT-IN SELF-TEST CIRCUIT AND TEMPERATURE MEASUREMENT CIRCUIT INCLUDING THE SAME
A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.
Method and device for wafer-level testing
The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
Power system component testing using a power system emulator-based testing apparatus
An apparatus for testing components for use in a power system includes at least one power amplifier circuit configured to be coupled to the component and a control circuit configured to operate the power amplifier circuit responsive to at least one state of a component emulator for the component included in a system emulator for the power system. The component emulator may include at least one power electronics converter circuit and the control circuit may be configured to control at least one of a voltage and a current of the at least one power amplifier circuit responsive to at least one of a voltage and a current of the at least one power electronics converter circuit. The control circuit may be further configured to control the component emulator responsive to at least one state of the at least one power amplifier circuit.
Systems and methods for PLP capacitor health check
Various implementations described herein relate to systems and methods for determining abnormal leakage current of a capacitor by determining a number of recent leakage current values for the capacitor and determining a maximum upper limit, minimum upper limit, maximum lower limit, and minimum lower limit based on leakage current values different from the recent leakage current values. A present upper limit and a present lower limit are determined for the recent leakage current values. Abnormal leakage current is determined in response to determining that the present upper limit being greater than an upper threshold (determined based on the maximum upper limit and the minimum upper limit) or the present lower limit being less than a lower threshold (determined based on the maximum lower limit and the minimum lower limit).