Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

A method includes mapping an AMC into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

An example process for aligning channels in automatic test equipment (ATE) includes programming a first delay associated with receiving first data over a channel so that timing of the channel is aligned to timings of other channels in the ATE; programming a second delay associated with a driver driving second data over the channel based on receipt of an edge of the second data so that timing of the second data is aligned to the timing of the channel; and programming a third delay associated with a signal to enable the driver to drive the second data over the channel, with the third delay being programmed to align timing of the signal to the timing of the channel, and with the third delay being based on an edge that corresponds to an edge of the signal created by controlling operation of the driver.

Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.

An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

A voltage droop monitor comprises an error detection circuit comprising a flip-flop, a latch, and a comparator configured to compare a first output of the flip-flop and a second output of the latch. A clock generator is configured to generate a flip-flop clock signal for the flip-flop and a latch clock signal for the latch based on a system clock signal, wherein the flip-flop clock signal and the latch clock signal are inverted and time-shifted with respect to each other, and wherein a triggering edge of the flip-flop clock is configured to occur after a termination of a triggering level of the latch clock signal. A pulse generator circuit is configured to generate a series of pulses. A data path connects an output of the pulse generator circuit to inputs of the flip-flop and the latch, the data path comprising one or more timing delay components.

An integrated circuit includes a ring oscillator circuit and a plurality of logic paths. Each logic path comprises a path input connection, a path output connection and an input multiplexer, which has an output connection that is connected to the path input connection of the logic path. Each logic path, beginning with a first logic path, is assigned a respective subsequent logic path by virtue of the path output connection of the logic path being connected to a data input connection of the input multiplexer of the subsequent logic path. A last logic path of the logic paths is assigned the first logic path as subsequent logic path. For each logic path, the multiplexer is configured such that, when a control signal that indicates a test mode is fed thereto, it connects the data input connection of the input multiplexer to the path input connection of the logic path.

An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.

A method of testing a semiconductor device includes: measuring minimum operating voltages of a plurality of semiconductor devices and operating frequencies of first and second ring oscillators included in the semiconductor devices, wherein the first ring oscillators have a first circuit configuration and the second ring oscillators have a second circuit configuration different from the first circuit configuration; generating a first model representing a correlation between operating frequencies of the first ring oscillators in the semiconductor devices and the minimum operating voltages of the semiconductor devices; generating a second model representing a correlation between operating frequencies of the second ring oscillators in the semiconductor devices and the minimum operating voltages of the semiconductor devices; measuring the operating frequencies of the first ring oscillators and the second ring oscillators included in a target semiconductor device; calculating a first measurement value using the operating frequencies of the first ring oscillators in the target semiconductor device and the first model; calculating a second measurement value using the operating frequencies of the second ring oscillators in the target semiconductor device and the second model; determining a high temperature compensation voltage of the target semiconductor device based on the first measurement value and the second measurement value; and modifying a dynamic voltage and frequency scaling (DVFS) table of the target semiconductor device according to the high temperature compensation voltage.