A benchmark device and a method for evaluating a semiconductor wafer are provided. The benchmark device includes a first grating coupler, a second grating coupler and a waveguide. The waveguide has a least one bending section and is arranged in communication with the first grating coupler and the second grating coupler. The bending section comprises a first region having a first width and a first height, and a second region having a second width and a second height, wherein the first region is surrounded by the second region, and the second width decreases gradually from a first end of the bending section to a second end of the bending section.

A benchmark device and a method for evaluating a semiconductor wafer are provided. The benchmark device includes a first grating coupler, a second grating coupler and a waveguide. The waveguide has a least one bending section and is arranged in communication with the first grating coupler and the second grating coupler. The bending section comprises a first region having a first width and a first height, and a second region having a second width and a second height, wherein the first region is surrounded by the second region, and the second width decreases gradually from a first end of the bending section to a second end of the bending section.

Data indicative of location information of a potential defect of interest revealed in a specimen and of one or more layers of the specimen corresponding to the potential defect of interest may be received. A die layout clip may be generated in accordance with the data by deriving the die layout clip based on the location information of the potential defect of interest and the one or more layers of the specimen corresponding to the potential defect of interest. The die layout clip may include information indicative of one or more patterns characterizing an inspection area that includes the potential defect of interest of the specimen. The generated die layout clip may be transmitted to a semiconductor inspection unit where an inspection by the semiconductor inspection unit of a semiconductor wafer that includes the specimen corresponding to the potential defect of interest is based on the one or more patterns of the die layout clip.

A semiconductor device inspection apparatus is an apparatus for inspecting a semiconductor device which is an object to be inspected based on a result signal which is output in accordance with input of a test pattern signal to the semiconductor device, the apparatus including: an ultrasonic transducer, disposed to face the semiconductor device, which generates ultrasonic waves; a stage for moving a relative position of the semiconductor device and the ultrasonic transducer; a stimulation condition control unit for controlling a condition of stimulation by the ultrasonic waves applied to the semiconductor device; and an analysis unit for generating a measurement image based on the result signal which is output from the semiconductor device.

An interconnect circuit testing apparatus including: an electric signal generating circuit for generating an electric signal; a first electrode arranged at a first region of a substrate, wherein the substrate includes an interconnect circuit, an upper surface and a lower surface; a second electrode arranged at a second region of the substrate; and a sensor for detecting an electric field emitted from the first region or the second region when the electric signal is applied to the substrate through the first electrode and the second electrode.

The invention relates to an integrated circuit with an active transistor area and a plurality of wiring layers arranged above the active transistor area. At least one optical device is integrated in the active transistor area. The optical device is electrically connected with at least one of the wiring layers. At least one optical tunnel extends from the at least one optical device through the plurality of wiring layers to a surface of an uppermost wiring layer of the plurality of wiring layers facing away from the active transistor area.

A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. The scanning system is configured to updated the time-dependent map of the emissions based on a transformation of an underlying time-resolved waveform at certain intervals and corresponding to at least one location and generating a pseudo image of the DUT.

As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of an electrode pad of a TEG to facilitate the evaluation of electrical characteristics. According to the present invention, the above described problem can be solved by arranging a plurality of probes in a fan shape or manufacturing the probes with micro electro mechanical systems (MEMS) technology.

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas.

A wireless test system includes a load board having an upper surface and a lower surface. The load board has a testing antenna disposed on the load board. A socket for receiving a device under test (DUT) having an antenna structure therein is disposed on the upper surface of the load board. The antenna structure is aligned with the testing antenna. The wireless test system further includes a handler for picking up and delivering the DUT to the socket. The handler has a clamp for holding and pressing the DUT. The clamp is grounded during testing and functions as a ground reflector that reflects and reverses radiation pattern of the DUT from an upward direction to a downward direction toward the testing antenna.