An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

Embodiments may relate an x-ray filter. The x-ray filter may be configured to be positioned between an x-ray source output and a device under test (DUT) that is to be x-rayed. The x-ray filter may include at least 80% titanium (Ti) by weight. Other embodiments may be described or claimed.

Embodiments may relate an x-ray filter. The x-ray filter may be configured to be positioned between an x-ray source output and a device under test (DUT) that is to be x-rayed. The x-ray filter may include at least 80% titanium (Ti) by weight. Other embodiments may be described or claimed.

An integrated circuit is fabricated on a semiconductor material die and adapted to be at least partly tested wirelessly. Circuitry for setting a selected radio communication frequency to be used for the wireless test of the integrated circuit is integrated on the semiconductor material die.

An integrated circuit is fabricated on a semiconductor material die and adapted to be at least partly tested wirelessly. Circuitry for setting a selected radio communication frequency to be used for the wireless test of the integrated circuit is integrated on the semiconductor material die.

A semiconductor storage device, an operating method thereof, and an analysis system capable of analyzing a defect during a specific operation is provided. A semiconductor chip provided by the disclosure determines that whether the semiconductor storage device is in a power-on mode based on a voltage supplied to an external terminal and executes a power-on sequence when the semiconductor storage device is in the power-on mode. The semiconductor chip then determines that whether execution of a break sequence is set, and if the execution is set, the semiconductor chip executes the break sequence. In the break sequence, a selected operation is executed, so that an operation being executed is stopped at a selected timing. A defect of the semiconductor chip is analyzed in a stopped state.

A semiconductor storage device, an operating method thereof, and an analysis system capable of analyzing a defect during a specific operation is provided. A semiconductor chip provided by the disclosure determines that whether the semiconductor storage device is in a power-on mode based on a voltage supplied to an external terminal and executes a power-on sequence when the semiconductor storage device is in the power-on mode. The semiconductor chip then determines that whether execution of a break sequence is set, and if the execution is set, the semiconductor chip executes the break sequence. In the break sequence, a selected operation is executed, so that an operation being executed is stopped at a selected timing. A defect of the semiconductor chip is analyzed in a stopped state.

Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (NCEM) of fill cells that contain structures configured target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such processes may involve evaluating Designs of Experiments (DOEs), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

This ultrasonic inspection device, for inspecting a packaged semiconductor device, is provided with: an ultrasonic transducer which outputs ultrasonic waves to a semiconductor device; a receiver (a reflection detection unit) which detects reflected waves of the ultrasonic waves reflected on the semiconductor device; a stage which moves the positions of the semiconductor device relative to the ultrasonic transducer; a stage control unit which controls driving of the stage; and an analysis unit which analyzes the reaction of the semiconductor device to the input of the ultrasonic waves from the ultrasonic transducer. The stage control unit controls the distance between the semiconductor device and the ultrasonic transducer on the basis of a peak occurring in time waveform of the reflected wave detected by the receiver.