The invention relates to a method for the contactless tapping of communication signals that are exchanged between two communication units, in particular a sensor or actuator and a digital evaluating or control unit, wherein the communication signals are transmitted on a line (2) of a multi-core cable (1) as voltage signals. According to the invention, in order that the communication signals can be tapped also in the case of multi-core cables without the line having to be interrupted for this purpose, the communication signals are tapped capacitively, wherein at least two electrodes (10a, 10b), which lie on the cable sheath and the angular position of which in relation to the cable axis is variable, are used for the tapping and the angular position at which the differential signal between the two electrodes (10a, 10b) is maximized is determined, wherein the at least two electrodes (10a, 10b), each consisting of a plurality of individual electrodes (E1-E8), are designed as collection electrodes and the various angular positions of the collection electrodes (10a, 10b) are achieved in that the association of the individual electrodes (E1-E8) with the at least two collection electrodes (10a, 10b) is sequentially changed by means of a controller (26). The invention further relates to an assembly for performing said method.

The invention relates to a method for the contactless tapping of communication signals that are exchanged between two communication units, in particular a sensor or actuator and a digital evaluating or control unit, wherein the communication signals are transmitted on a line (2) of a multi-core cable (1) as voltage signals. According to the invention, in order that the communication signals can be tapped also in the case of multi-core cables without the line having to be interrupted for this purpose, the communication signals are tapped capacitively, wherein at least two electrodes (10a, 10b), which lie on the cable sheath and the angular position of which in relation to the cable axis is variable, are used for the tapping and the angular position at which the differential signal between the two electrodes (10a, 10b) is maximized is determined, wherein the at least two electrodes (10a, 10b), each consisting of a plurality of individual electrodes (E1-E8), are designed as collection electrodes and the various angular positions of the collection electrodes (10a, 10b) are achieved in that the association of the individual electrodes (E1-E8) with the at least two collection electrodes (10a, 10b) is sequentially changed by means of a controller (26). The invention further relates to an assembly for performing said method.

A test apparatus includes test probes for exchanging electrical signals with terminals of an electronic device under test. The test probes form a capacitive electromagnetic coupling connection with the terminals.

Multiple planes within the sample are exposed from a single perspective for contact by an electrical probe. The sample can be milled at a non-orthogonal angle to expose different layers as sloped surfaces. The sloped edges of multiple, parallel conductor planes provide access to the multiple levels from above. The planes can be accessed, for example, for contacting with an electrical probe for applying or sensing a voltage. The level of an exposed layer to be contacted can be identified, for example, by counting down the exposed layers from the sample surface, since the non-orthogonal mill makes all layers visible from above. Alternatively, the sample can be milled orthogonally to the surface, and then tilted and/or rotated to provide access to multiple levels of the device. The milling is preferably performed away from the region of interest, to provide electrical access to the region while minimizing damage to the region.

A test system and method for identifying open and shorted connections on a printed circuit board (PCB). An integrated circuit (IC) unit on the PCB is configured to generate a test signal on an output pin connected to a test pin on a second device, connector, or socket on the PCB. For a connection, the test signal is capacitively coupled to a detector plate proximal the second device. Based on the signal coupled to the detector, time domain analysis is performed on the coupled signal to determine if the test pin has a good connection to the PCB or if the pin is open or shorted. Analysis may include cross-correlating the coupled signal with a learned signal obtained from a known good PCB. The test pin may pass the test if the cross-correlation is within a specified threshold window. If the test fails, additional tests may be performed to troubleshoot the cause of the testing failure.

A test system and method for identifying open and shorted connections on a printed circuit board (PCB). An integrated circuit (IC) unit on the PCB is configured to generate a test signal on an output pin connected to a test pin on a second device, connector, or socket on the PCB. For a connection, the test signal is capacitively coupled to a detector plate proximal the second device. Based on the signal coupled to the detector, time domain analysis is performed on the coupled signal to determine if the test pin has a good connection to the PCB or if the pin is open or shorted. Analysis may include cross-correlating the coupled signal with a learned signal obtained from a known good PCB. The test pin may pass the test if the cross-correlation is within a specified threshold window. If the test fails, additional tests may be performed to troubleshoot the cause of the testing failure.

An embodiment of a test apparatus for executing a test of a set of electronic devices having a plurality of electrically conductive terminals, the test apparatus including a plurality of electrically conductive test probes for exchanging electrical signals with the terminals, and coupling means for mechanically coupling the test probes with the electronic devices. In an embodiment, the coupling means includes insulating means for keeping each one of at least part of the test probes electrically insulated from at least one corresponding terminal during the execution of the test. Each test probe and the corresponding terminal form a capacitor for electro-magnetically coupling the test probe with the terminal.

Current Voltage and Capacitance Voltage (IV and CV) measurements are critical in measurement of properties of electronic materials especially semiconductors. A semiconductor testing device to accomplish IV and CV measurement supports a semiconductor wafer and provides a probe for contacting a surface on the wafer under control of an atomic Force Microscope or similar probing device for positioning the probe to a desired measurement point on the wafer surface. Detection of contact by the probe on the surface is accomplished and test voltage is supplied to the semiconductor wafer. A first circuit for measuring capacitance sensed by the probe based on the test voltage and a complimentary circuit for measuring Fowler Nordheim current sensed by the probe based on the test voltage are employed with the probe allowing the calculation of characteristics of the semiconductor wafer based on the measured capacitance and Fowler Nordheim current.

Current Voltage and Capacitance Voltage (IV and CV) measurements are critical in measurement of properties of electronic materials especially semiconductors. A semiconductor testing device to accomplish IV and CV measurement supports a semiconductor wafer and provides a probe for contacting a surface on the wafer under control of an atomic Force Microscope or similar probing device for positioning the probe to a desired measurement point on the wafer surface. Detection of contact by the probe on the surface is accomplished and test voltage is supplied to the semiconductor wafer. A first circuit for measuring capacitance sensed by the probe based on the test voltage and a complimentary circuit for measuring Fowler Nordheim current sensed by the probe based on the test voltage are employed with the probe allowing the calculation of characteristics of the semiconductor wafer based on the measured capacitance and Fowler Nordheim current.

A probe assembly includes plural capacitive contacts that are separate from each other and a conductive depletion gate disposed between and separating the contacts from each other. The depletion gate is configured to receive a direct electric voltage to deplete regions of a sample under test of electrons. The contacts are configured to be placed in close proximity to a buried conducting layer in the sample under test without engaging the buried conducting layer, thereby capacitively coupling to the buried conducting layer. A first subset of the capacitive contacts is configured to apply an alternating electric current to a portion of the sample under test and a second subset of the capacitive contacts is configured to sense an alternating voltage response of the portion of the sample under test to characterize one or more electrical properties of the sample under test without the capacitive contact with the buried conductive layer.