A vector-valued regularized kernel function approximation (VVRKFA) based fault diagnosis method for an analog circuit comprises the following steps: (1) obtaining fault response voltage signals of an analog circuit; (2) performing wavelet packet transform on the collected signals, and calculating wavelet packet coefficient energy values as feature parameters; (3) optimizing regularization parameters and kernel parameters of VVRKFA by using a quantum particle swarm optimization algorithm and training a fault diagnosis model; and (4) identifying a circuit fault by using the trained diagnosis model. In the invention, the classification performance of the VVRKFA method is superior to other classification algorithms, and optimization of parameters by the quantum particle swarm optimization (QPSO) algorithm is also superior to the traditional method of obtaining parameters. The fault diagnosis method provided by the invention can efficiently diagnose the component faults of the circuit, including soft faults and hard faults.

A vector-valued regularized kernel function approximation (VVRKFA) based fault diagnosis method for an analog circuit comprises the following steps: (1) obtaining fault response voltage signals of an analog circuit; (2) performing wavelet packet transform on the collected signals, and calculating wavelet packet coefficient energy values as feature parameters; (3) optimizing regularization parameters and kernel parameters of VVRKFA by using a quantum particle swarm optimization algorithm and training a fault diagnosis model; and (4) identifying a circuit fault by using the trained diagnosis model. In the invention, the classification performance of the VVRKFA method is superior to other classification algorithms, and optimization of parameters by the quantum particle swarm optimization (QPSO) algorithm is also superior to the traditional method of obtaining parameters. The fault diagnosis method provided by the invention can efficiently diagnose the component faults of the circuit, including soft faults and hard faults.

A force-sense system for providing signals to, or receiving signals from, a device under test (DUT) at a first DUT node. The system can include an interface coupling first and second portions of a first force-sense measurement device, such as a parametric measurement unit. The first and second portions of the first force-sense measurement device can be provided using respective different integrated circuits, such as can comprise different semiconductor dies of different die types. In a first test mode, the interface can be configured to communicate a first DUT force signal from the first portion to the second portion of the first force-sense measurement device, and in a second test mode the interface can be configured to communicate DUT sense information, received from the DUT at the first DUT node, from the second portion to the first portion of the first force-sense measurement device.

A vector-valued regularized kernel function approximation (VVRKFA) based fault diagnosis method for an analog circuit comprises the following steps: (1) obtaining fault response voltage signals of an analog circuit; (2) performing wavelet packet transform on the collected signals, and calculating wavelet packet coefficient energy values as feature parameters; (3) optimizing regularization parameters and kernel parameters of VVRKFA by using a quantum particle swarm optimization algorithm and training a fault diagnosis model; and (4) identifying a circuit fault by using the trained diagnosis model. In the invention, the classification performance of the VVRKFA method is superior to other classification algorithms, and optimization of parameters by the quantum particle swarm optimization (QPSO) algorithm is also superior to the traditional method of obtaining parameters. The fault diagnosis method provided by the invention can efficiently diagnose the component faults of the circuit, including soft faults and hard faults.

A vector-valued regularized kernel function approximation (VVRKFA) based fault diagnosis method for an analog circuit comprises the following steps: (1) obtaining fault response voltage signals of an analog circuit; (2) performing wavelet packet transform on the collected signals, and calculating wavelet packet coefficient energy values as feature parameters; (3) optimizing regularization parameters and kernel parameters of VVRKFA by using a quantum particle swarm optimization algorithm and training a fault diagnosis model; and (4) identifying a circuit fault by using the trained diagnosis model. In the invention, the classification performance of the VVRKFA method is superior to other classification algorithms, and optimization of parameters by the quantum particle swarm optimization (QPSO) algorithm is also superior to the traditional method of obtaining parameters. The fault diagnosis method provided by the invention can efficiently diagnose the component faults of the circuit, including soft faults and hard faults.

In-chip decoupling capacitor circuits refer to decoupling capacitors (DCAPs) that are placed on a chip. These DCAPs are generally used to manage power supply noise for the chip, and can be utilized individually or as a distributed system. In some cases, DCAPs may make up a significant portion of the chip. Unfortunately, defects in DCAPs will degrade over time, will encroach into active logic, and will further cause automatic test pattern generation (ATPG) failure. To date, there has been a lack of structural test coverage for DCAP circuits, which reduces test coverage of the chip as a whole. To this end, defects on the chip as they relate to DCAPs (i.e. shorts in the DCAP) may not be detected. The present disclosure provides a structural test system and method for DCAPs and other passive logic components located on-chip.

The disclosure discloses an analog circuit fault feature extraction method and system based on an optimal wavelet basis function, and belongs to the field of electronic circuit engineering and computer vision, and the method comprises the steps of obtaining output signals of an analog circuit during different faults; sequentially applying wavelet transformation methods based on different wavelet basis functions to extract features of output signals; for each feature, calculating the center position of each fault, the distance from each fault data point to the center position, the farthest position of the fault data point and the average position of the fault data points; and determining an optimal wavelet basis function for analog circuit fault feature extraction according to a score discriminating method.

When testing a reset circuit, a first register outputs a set signal to an OR circuit of the reset circuit so that a logic circuit is not reset even if an input voltage is low. Further, when testing the reset circuit, the first register turns off a regulator circuit by outputting a set signal from a second register to the regulator circuit and supplying the input voltage to the reset circuit from an external device via a voltage application terminal. Subsequently, the input voltage supplied from the voltage application terminal is varied and an output signal of a comparator output from a signal output circuit through an external terminal is checked to test whether the reset circuit is actuated normally.

When testing a reset circuit, a first register outputs a set signal to an OR circuit of the reset circuit so that a logic circuit is not reset even if an input voltage is low. Further, when testing the reset circuit, the first register turns off a regulator circuit by outputting a set signal from a second register to the regulator circuit and supplying the input voltage to the reset circuit from an external device via a voltage application terminal. Subsequently, the input voltage supplied from the voltage application terminal is varied and an output signal of a comparator output from a signal output circuit through an external terminal is checked to test whether the reset circuit is actuated normally.

An example analog-test-bus (ATB) apparatus includes a plurality of comparator circuits, each having an output port, and a pair of input ports of opposing polarity including an inverting port and a non-inverting port, a plurality of circuit nodes to be selectively connected to the input ports of a first polarity, and at least one digital-to-analog converter (DAC) to drive the input ports of the plurality of comparator circuits. The apparatus further includes data storage and logic circuitry that accounts for inaccuracies attributable to the plurality of comparator circuits by providing, for each comparator circuit, a set of calibration data indicative of the inaccuracies for adjusting comparison operations performed by the plurality of comparator circuits.