A power source emulator is provided for testing programmable switchgear that switches to an alternative three-phase power source upon sensing a failure of a grid source. The emulator provides three simulated three-phase power sources for testing switchgear. Each source is identical in voltage and phase to the current normally distributed by the switchgear but has less than 1% of the amperage. Each power source includes a single three-phase contactor for simultaneously controlling all three phases of the power source, and three solid-state relays for controlling each of the three phases of the power source. A control circuit controls the three-phase contactor and each of the three solid state relays of each power source to simulate various types of power failures that the switchgear is programmed to respond to.

A power source emulator is provided for testing programmable switchgear that switches to an alternative three-phase power source upon sensing a failure of a grid source. The emulator provides three simulated three-phase power sources for testing switchgear. Each source is identical in voltage and phase to the current normally distributed by the switchgear but has less than 1% of the amperage. Each power source includes a single three-phase contactor for simultaneously controlling all three phases of the power source, and three solid-state relays for controlling each of the three phases of the power source. A control circuit controls the three-phase contactor and each of the three solid state relays of each power source to simulate various types of power failures that the switchgear is programmed to respond to.

A divider circuit includes an analog divider circuit with pre-load circuitry configured to allow for a programmable starting value. The circuit is responsive, synchronous with a divider clock, to count from the starting value, and includes an observation bus that outputs a current count value of the analog divider circuit. The divider circuit further includes test clock logic configured, in a divider circuit test mode, to be responsive to a reference clock to output the divider clock to clock the analog divider circuit for a number of clock cycles corresponding to a programmable test clock length.

A divider circuit includes an analog divider circuit with pre-load circuitry configured to allow for a programmable starting value. The circuit is responsive, synchronous with a divider clock, to count from the starting value, and includes an observation bus that outputs a current count value of the analog divider circuit. The divider circuit further includes test clock logic configured, in a divider circuit test mode, to be responsive to a reference clock to output the divider clock to clock the analog divider circuit for a number of clock cycles corresponding to a programmable test clock length.

A variable-bit adaptive sensing circuit system in an analog neuromorphic system is disclosed. In an analog neuromorphic system including a synapse array, the circuit system for sensing the synapse array comprises: a sensing part circuit configured to sense output currents of synapse devices in each column of the synapse array in response to an operation signal; an error detection circuit configured to detect errors based on the column-wise output currents of the synapse devices and determine an operation start reference; and an analog-to-digital conversion circuit configured to integrate the synapse device current based on the operation start reference, convert the integrated current into a voltage value, and output a corresponding digital value.

A variable-bit adaptive sensing circuit system in an analog neuromorphic system is disclosed. In an analog neuromorphic system including a synapse array, the circuit system for sensing the synapse array comprises: a sensing part circuit configured to sense output currents of synapse devices in each column of the synapse array in response to an operation signal; an error detection circuit configured to detect errors based on the column-wise output currents of the synapse devices and determine an operation start reference; and an analog-to-digital conversion circuit configured to integrate the synapse device current based on the operation start reference, convert the integrated current into a voltage value, and output a corresponding digital value.

Apparatuses, systems, and methods for, and more particularly to apparatuses, systems, and methods for a high-speed composite amplifier driving circuit to generate and output analog signals. The high-speed composite amplifier driving circuit can combine a voltage-controlled pulser and waveform generator with high-accuracy current-voltage (I-V) measurement functions. The voltage-controlled pulser and waveform generator, for example, can provide a 5 volt, 10 milliamp waveform at up to 50 megahertz with 5 nanosecond rise/fall timing and 8 ns minimum pulse widths. In addition, the high-accuracy I-V measurements can measure a 10 volts, 10 milliamp waveform at up to 30 MHz with 7-10 nanosecond rise/fall timing and 8 to 12 nanosecond minimum pulse widths.

Apparatuses, systems, and methods for, and more particularly to apparatuses, systems, and methods for a high-speed composite amplifier driving circuit to generate and output analog signals. The high-speed composite amplifier driving circuit can combine a voltage-controlled pulser and waveform generator with high-accuracy current-voltage (I-V) measurement functions. The voltage-controlled pulser and waveform generator, for example, can provide a 5 volt, 10 milliamp waveform at up to 50 megahertz with 5 nanosecond rise/fall timing and 8 ns minimum pulse widths. In addition, the high-accuracy I-V measurements can measure a 10 volts, 10 milliamp waveform at up to 30 MHz with 7-10 nanosecond rise/fall timing and 8 to 12 nanosecond minimum pulse widths.

An RF testing method is applied between a testing instrument and multiple devices under test at least including a first DUT and a second DUT. The testing instrument includes a signal generator and a signal analyzer. A sync signal is sent to the testing instrument and the first DUT, so that the first DUT occupies the signal generator to receive a testing signal from the signal generator. The first DUT sends an uplink signal to the signal analyzer based on the testing signal to occupy the signal analyzer for signal analysis at a first point in time. The sync signal is sent to the testing instrument and the second DUT, so that the second DUT occupies the signal generator to receive the testing signal from the signal generator at a second point in time. The first point in time is parallel to the second point in time.

An RF testing method is applied between a testing instrument and multiple devices under test at least including a first DUT and a second DUT. The testing instrument includes a signal generator and a signal analyzer. A sync signal is sent to the testing instrument and the first DUT, so that the first DUT occupies the signal generator to receive a testing signal from the signal generator. The first DUT sends an uplink signal to the signal analyzer based on the testing signal to occupy the signal analyzer for signal analysis at a first point in time. The sync signal is sent to the testing instrument and the second DUT, so that the second DUT occupies the signal generator to receive the testing signal from the signal generator at a second point in time. The first point in time is parallel to the second point in time.