Patent classifications
G
G01
G01R
31/00
G01R31/28
G01R31/317
G01R31/31702
G01R31/31702
3D INTEGRATED CIRCUIT WITH ENHANCED DEBUGGING CAPABILITY
An integrated circuit includes a plurality of layers. A subset of the plurality of layers is reserved for implementing user circuitry. At least a portion of a selected layer of the plurality of layers is reserved for debugging.