Provided is an apparatus including a generating section that generates an altered test candidate obtained by adding an alteration shortening an execution time of a test to a target test for testing a device under test; a test processing section that causes a test apparatus to perform the altered test candidate on the device under test; and a comparing section that compares an altered test result of the device under test resulting from the altered test candidate to a target test result of the device under test resulting from the target test; and a judging section that judges whether the target test can be replaced by the altered test candidate, based on the comparison result of the comparing section.

According to one embodiment, a semiconductor device includes a control circuit configured to generate a first signal and a second signal, a gating circuit configured to execute supply or stoppage of supply of a clock signal based on the first signal, and a circuit block configured to accept the clock signal, the second signal, and a test pattern. The gating circuit is configured to execute resupply of the clock signal after the stoppage of the supply, based on the first signal during a period of a scan test.

According to one embodiment, a semiconductor integrated circuit includes: a first core that includes a first logic circuit that has a plurality of first scan chains, and a first generator that generates a first test pattern; a second core that includes a second logic circuit that has a plurality of second scan chains, and a second generator that generates a second test pattern; a controller that controls a test operation of the first and second cores. The controller is configured to: obtain a seed for a test pattern from the first generator; supply the obtained seed to the second generator; perform a test on the first and second cores for a same number of cycles; obtain first and second test results respectively from the first and second cores; and compare the first and second test results.

A memory device includes; a memory cell array including memory cells, a row decoder selecting a word line in response to a received address, and control logic including a sensing capacitor having a size proportional to a size of a word line capacitor associated with the selected word line. The control logic measures line resistance of the selected word line by precharging the selected word line, performing a charge sharing operation between the selected word line and the sensing capacitor following the precharging of the selected word line, and measuring a voltage of the sensing capacitor following the performing of the charge sharing operation.

An electronic device such as an e-fuse includes analog circuitry configured to be set to one or more self-test configurations. To that effect the device has self-test controller circuitry in turn including: an analog configuration and sensing circuit configured to set the analog circuitry to one or more self-test configurations and to sense test signals occurring in the analog circuitry set to such self-test configurations, a data acquisition circuit configured to acquire and convert to digital the test signals sensed at the analog sensing circuit, and a fault event detection circuit configured to check the test signals converted to digital against reference parameters. The device includes integrated therein a self-test controller configured to control parts or stages of the device to configure circuits, acquire data and control test execution under the coordination of a test sequencer.

Various embodiments provide for testing a transmitter with interpolation, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer over a plurality of different interpolation phase positions of a phase interpolator; and using a pattern checker to error check the sampled data over the plurality of different interpolation phase positions to determine whether the data transmission test passes.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.