A method of testing an electronic unit by comparing resulting signal shapes from the unit to be tested and a known functioning unit. The method includes powering off the units for testing and feeding one or more predefined signal shapes of two or more different frequencies as input signals to the known functioning unit and to the unit to be tested at corresponding test points. The method further includes measuring the resulting signal shapes from both units at corresponding measurement points and comparing at least one resulting signal shape from the known functioning unit with the corresponding resulting signal shape from the unit to be tested. The method also includes detecting a fault in the unit to be tested on the basis of an existing signal shape distortion in time axis of the resulting signal shape received from the unit to be tested.

Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.

A method for compliance testing of a Digital Interface Board attached to Automatic Test Equipment in the testing of integrated circuit semiconductor devices using Impedance Response Profiling. The includes launching alternating voltage digital clock signals from the Pin Electronics to one or more circuit paths in the Digital Interface Board, and sampling a mix of the launched alternating voltage digital clock signals and reflected signals. The method also includes compositing time domain waveforms originating at the Pin Electronics, and generating an initial reflection response profile baseline. The method is repeated at a later predetermined time, generating a later reflection response profile. The method further includes comparing the initial reflection response profile baseline with the later reflection response profile, and determining whether the one or more circuit paths of the Digital Interface Board are in compliance with predetermined operating standards.

According to one or more embodiments, the semiconductor integrated circuit device includes a pattern generator, a result comparator, and a control circuit. The pattern generator supplies input data to a device-under-test. The result comparator compares output data of the device-under-test with expected value data and outputs a test result signal. The control circuit controls the pattern generator and the result comparator. The device-under-test and the result comparator are commonly connected to a first clock line. The pattern generator and the control circuit are commonly connected to a second clock line different from the first clock line.

A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.

A device for a system on a chip (SOC), the device includes: a comparator that includes a first input port, a second input port, and an output port. A first input signal and a second input signal are split into N bit pairs that include one bit from the first input signal and one bit from the second input signal. The comparator is configured so a mismatch between the first input signal and the second input signal causes an output signal to assume a first expected state. The device further comprises a test controller to perform a first operability test by mismatching the N bit pairs and verifying that the output signal assumes the first expected state.

Accordingly, an improved interposer connection testing technique is provided, employing parallel pseudo-random bit sequence (PRBS) generators to test all the interconnects in parallel and simultaneously detect any correctable defects. In one embodiment, a microelectronic assembly includes an interposer electrically connected in a flip-chip configuration to an originating IC (integrated circuit) die and to a destination IC die, the substrate having multiple conductive traces for a parallel communications bus between the IC dies. The originating IC die has a first parallel PRBS (pseudo-random binary sequence) generator to drive test PRBSs with different phases in parallel across the interposer traces. The destination IC die has a second parallel PRBS generator to create reference PRBSs with different phases, and a bitwise comparator coupled to receive the test PRBSs from the interposer traces and to compare them to the reference PRBSs to provide concurrent fault monitoring for each of the traces.

Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

The disclosure relates to monitoring of feedback systems such as phase lock loops. A system is disclosed, comprising: a feedback circuit (100); and a monitoring module (190). The monitoring module (190) is configured to: i) receive actual values of at least one state variable describing the state of the feedback circuit at a first time; ii) determine a predicted future value of the at least one state variable at a second time from the actual values at the first time using a model of the feedback circuit; iii) receive actual values of the at least one state variable at the second time; iv) compare the predicted future value of the at least one state variable at the second time with the actual value of the at least one state variable at the second time; and v) determine whether the feedback circuit has a fault condition, depending on the results of step iv).