Disclosed are a chip verification method and apparatus, an electronic device, and a storage medium. The method includes: obtaining data traffic mode information of a design under test of a chip in a target scenario; determining a data traffic feature corresponding to the design under test based on the data traffic mode information; constructing excitation corresponding to the design under test based on the data traffic feature; and verifying the design under test based on the excitation, to obtain a verification result of the design under test in the target scenario. According to the embodiments of this disclosure, a service scenario of the design under test can be replicated on a verification platform, so that effective verification can be performed on a work condition of the design under test in the service scenario, without constructing complex cases for scenario verification, thereby greatly improving effectiveness of scenario verification.

An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.

Systems and methods of debugging a design under test for metastability issues using formal verification. In one aspect, the method includes determining, by a server, that a functionality of the DUT failed an assertion; generating, by the server, a plurality of first waveforms for a plurality of clock domain crossing (CDC) pairs that are in a cone of influence of the assertion; applying, by the server, a constraint including a condition to the plurality of waveforms; and generating, by the server, one or more second waveforms for a first subset of the plurality of CDC pairs, wherein the first subset of the CDC pairs satisfied the condition.

An electronic component comparison apparatus is disclosed for comparing performance characteristics of the electronic components at different operating conditions. The electronic component comparison apparatus includes a processor that receives input of a first electronic component and a first operating condition and receives input of a second electronic component and a second operating condition where the second operating condition may be different from the first operating condition. The processor estimates a first electronic component performance characteristic based at least in part on the first electronic component and the first operating condition and estimates a second electronic component performance characteristic based at least in part on the second electronic component and the second operating condition. The processor outputs the first electronic component performance characteristic and second electronic component performance characteristic via a user interface for comparison.

System, method for circuit validation, and system and method for facilitating circuit validation are provided. The circuit validation system comprises a prototype system and a computing device. The prototype system comprises a programming logic device circuit configured to implement a modified circuit design. The modified circuit design includes a circuit module as a design under test (DUT), an input generation circuit coupled to the circuit module for outputting input signals to the circuit module in response to a test signal, and an output acquisition circuit coupled to the circuit module for storing output data from the circuit module. The computing device is capable of being coupled to the prototype system and configured to generate the test signal to perform a test of the DUT on the prototype system.

The Translation Layer is embedded into each circuit under test (CUT) to modularize test process. The modularized tests are self-contained and performed in isolation. They are composed without consideration of environment constraints. The CUT and its environment constraints can be concurrently be tested in isolation and independently. Interconnections between the CUT and the environment can be tested in the environment constraint test without additional dedicated test logic. The modularized test process allows the test patterns of the environment constraints to be derived from those of the CUT. The resulting test patterns are used to compose the test patterns of a target system. Since the test process is recursive in nature, the modularized test of each constituent subsystem or design core can be performed in isolation in the target system, while the environment constraints and the interconnections are being tested concurrently.

This application discloses a computing system implementing a schematic capture tool to utilize physical test capabilities of a manufacturer of a printed circuit board assembly during generation of a logical design for the printed circuit board assembly. The schematic capture tool can utilize the physical test capabilities of the manufacturer to trim a list of parts representing electronic components available for use in the printed circuit board assembly, and generate the logical design for the printed circuit board assembly utilized the trimmed list of parts. The schematic capture tool can utilize the physical test capabilities of the manufacturer to determine which nets in the logical design to assign test points. The schematic capture tool can provide an indication of the assigned test points to a layout tool, which can include the test points in a layout design for the printed circuit board assembly based on the assignment.

Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.

A sequential circuit includes a data input terminal, a data path, and a redundant feedback loop. The data input terminal receives input data. The data path is connected to the data input terminal and transmits the input data to a data output terminal based on a first clock signal and a second clock signal. The redundant feedback loop is connected to the first data path and stores first data based on at least one of the first or second clock signals when the first data is equal to second data. The first data corresponds to the input data. The second clock signal is a delayed signal of the first clock signal. The second data is delayed data of the first data.

Adjustable integrated circuits and methods for designing the same are provided. In one embodiment, a method of designing an integrated circuit includes determining a plurality of design criteria of the integrated circuit; designing a plurality of circuit blocks of the integrated circuit in accordance with the plurality of design criteria, where one or more circuit blocks in the plurality of circuit blocks include one or more feedback paths; designing a circuit performance monitor, where the circuit performance monitor includes one or more replica feedback paths corresponding to the one or more feedback paths in the one or more circuit blocks, and where the circuit performance monitor is configured to monitor feedback path information of the one or more replica feedback paths; verifying the plurality of circuit blocks and the circuit performance monitor to meet the plurality of design criteria; and producing a verified description of the integrated circuit for manufacturing.