Determining simulation test coverage for a design of an electronic circuit, where graph-based verification tools are used to verify functional correctness of said design. A test coverage is determined from specified coverage points, and hardware test coverage is measured based on the occurrence of selected events. A specification for simulation test scenarios, and a hardware design language specification for the design comprising hardware events are provided. A list of event groups belonging to one simulation test scenario is created. For each group a temporal property coverage checker in the simulation model is generated that comprises a switch to enable or disable it.

Dynamic power-aware encoding method and apparatus is presented based on a various embodiments described herein. The experimental results confirmed that a desirable reduction in the toggling rate in the decompressed test stimulus is achievable by reasonable overhead (ATPG time, hardware overhead and pattern inflation) typically without degradation of a compression ratio. The performed experimental evaluation confirms that the described embodiments can support aggressive scan compression, efficient dynamic pattern compaction and a reduction of toggling rate in the decompressed test stimulus.

Various aspects of the disclosed technology relate to techniques of selecting scan cells from state elements for partial scan designs. Signal probability values for logic gates in a circuit design are first determined. Based on the signal probability values, next-state capture probability values for state elements in the circuit design are computed. Based on the next-state capture probability values, scan cells are selected from the state elements. Scan cells may be further selected based on continuously-updated control weight values and observation weight values associated with the state elements.

Aspects include a computer-implemented method for scan diagnostic logic circuit insertion in a circuit design topology. A method includes evaluating a scan chain of the circuit design topology, the scan chain comprising a plurality of scan latches and a plurality of physical structures, the evaluating including identifying the plurality of physical structures in the scan chain. The method also includes identifying one of the plurality of physical structures as a physical structure of interest, and responsive to the identification of the physical structure of interest, targeting the physical structure of interest, the targeting comprising inserting scan diagnostic logic at a location in the scan chain that is based on a location of the physical structure of interest in the scan chain.

Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.

A test system is provided for performing design for debug (DFD) operations. The test system may include a host processor coupled to an auxiliary device. The auxiliary device may include a protocol interface block for communicating with the host processor during normal functional mode. The auxiliary die may further include a circuit under test (CUT) and a hardened DFD hub that can be controlled by the host processor via the protocol interface block. The DFD hub may include a DFD triggering component, a DFD tracing component, and a DFD access component. The host processor may direct the DFD hub to perform DFD operations by sending control signals through the protocol interface block during a debugging mode. Test information gathered using the DFD hub may be fed back to the host processor to help facilitate silicon bring-up, pre-production software stack optimization, and post-production performance metric monitoring.

Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine observed failing bit patterns. Bit-reduction is performed on the observed failing bit patterns to construct first training samples. Using the first training samples, first-level machine-learning models are trained. Affine scan cell groups are identified. Second training samples are prepared for each of the affine scan cell groups by performing bit-filtering on a subset of the observed failing bit patterns associated with the faults being injected at scan cells in the each of the affine scan cell groups. Using the second training samples, second-level machine-learning models are trained. The first-level and second-level machine learning models can be applied in a multi-stage machine learning-based chain diagnosis process.

A method and circuit are provided for implementing enhanced scan data testing with over masking removal in an on product multiple input signature register plus (OPMISR+) test due to common Channel Mask Scan Registers (CMSRs) loading, and a design structure on which the subject circuit resides. An OPMISR plus satellite includes a multiple input signature register (MISR) for data collection and a plurality of associated scan channels. A common Channel Mask Scan Registers (CMSR) logic is used with the multiple input signature register (MISR). Unique CMSR data is loaded into at least one OPMISR plus satellite for implementing enhanced scan data testing. Scan pausing is used to reduce the amount of CMSR scan load data by loading the unique CMSR data only when needed.

This application discloses a computing system implementing a functional safety validation tool to simulate a circuit design having a digital portion and an analog portion, and inject a fault into the digital portion of a simulated circuit design, which propagates towards alarm logic configured to detect the injected fault. When the injected fault propagates to a boundary between the digital portion and the analog portion, the functional safety validation tool can perform a parallel simulation of the analog portion, which propagates the injected fault from the boundary through the analog portion to an output. The functional safety validation tool can determine whether the analog portion of the circuit design suppresses the injected fault based on a value at the output. The functional safety validation tool can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic based on whether the injected fault was suppressed.