According to one general aspect, an apparatus may include an interconnect bus, an interconnect-to-debug bus interface, and a debug bus. The interconnect bus may be configured to connect and manage combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock. The interconnect-to-debug bus interface may be configured to translate communications between the interconnect bus and the debug bus. The debug bus may include a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock. Each of the plurality of debug wrapper circuits may be configured to: identify if the respective debug wrapper circuit is activated by the debug bus, receive a non-invasive input from a respective combinatorial logic block, and place the non-invasive input from the respective combinatorial logic block on the debug bus.

Methods and systems for performing fault injection testing on an integrated circuit hardware design. The methods include: (a) receiving a raw fault node list identifying one or more fault nodes of the hardware design; (b) receiving information indicating a grouping of the fault nodes in the raw fault node list into a plurality of fault node groups, each fault node group comprising fault nodes that have a same effect on a failure mode of the hardware design; (c) generating a final fault node list based on the fault node groups; (d) selecting a set of fault injection parameters from the final fault node list, the set of fault injection parameters identifying at least one fault node in the final fault node list to fault; (e) performing a fault injection test on the hardware design by causing a fault to be injected into a simulation of the hardware design based on the selected set of fault injection parameters; (f) determining a result of the fault injection test; (g) storing the result of the fault injection test; and repeating (d) to (g) at least once.

A method for Design For Test (DFT) for Source Synchronous Interfaces (SSI) includes shifting a test vector into a master register slice with a DFT clock. A functional clock is generated. The test vector and the functional clock are launched from a first SSI of the master register slice. The test vector and the functional clock are captured with a second SSI of a slave. The test vector is shifted out of the slave with the DFT clock.

This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.

A method for debugging and a method for testing a circuit design on a programmable logic device is disclosed, making use of a parameterized configuration. A corresponding system also is disclosed.

Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Various aspects of the disclosed technology relate to circuit defect diagnosis based on sink cell fault models. Defect candidates are determined based on path-tracing from failing bits into the circuit design. Based on the defect candidates and one or more conventional fault models, failing test pattern simulations are performed to determine initial defect suspects. Initial defective sink cell suspects are then determined by comparing driving strengths for fan-out cells of the initial defect suspects with driving strengths for corresponding driver cells. Defective sink cell suspects may be identified in the initial defective sink cell suspects based on fault effect propagations and passing test pattern simulations.

According to certain aspects, the present embodiments relate to optimizing core wrappers in an integrated circuit to facilitate core-based testing of the integrated circuit. In some embodiments, an integrated circuit design flow is adjusted so as to increase the use of shared wrapper cells in inserted core wrappers, and to reduce the use of dedicated wrapper cells in such core wrappers, thereby improving timing and other integrated circuit design features. In these and other embodiments, the increased use of shared wrapper cells is performed even in the presence of shift registers in the integrated circuit design.

One embodiment provides a method and a system for computing diagnoses for a physical system. During operation, the system can obtain a design of the physical system, generate a design of a diagnostic system by augmenting the design of the physical system based on a number of fault-emulating subsystems, and convert the design of the diagnostic system into a polynomial formula comprising a plurality of variables. The plurality of variables can include inputs and outputs of the original physical system and a number of ancillary variables. The system can further embed the polynomial formula on a hardware-based solver configured to perform optimization using the polynomial formula as an objective function to obtain a diagnostic vector used for explaining faults in the physical system.

The approach disclosed herein is a new approach to sequence generation in the context of validation that relies on machine learning to explore and identify ways to achieve different states. In particular, the approach uses machine learning models to identify different states and ways to transition from one state to another. Actions are selected by machine learning models as they are being trained using reinforcement learning. This online inference also is likely to result in the discovery of not yet discovered states. Each state that has been identified is then used as a target to train a respective machine learning model. As part of this process a representation of all the states and actions or sequences of actions executed to reach those states is created. This representation, the respective machine learning models, or a combination thereof can then be used to generate different test sequences.