A computer implemented method, and an apparatus, are provided for performing a scalability check on a Hardware Description Language (HDL) representation of a circuit. The HDL representation identifies a plurality of sink signals, where each sink signal is arranged to take a result value computed by performing an operation using as input one or more driver signals. The method comprises creating within a storage a mapping table to map drivers signals to sink signals, where each entry identifies a sink signal and an associated sink width indication, identifies each driver signal used in the computation of the result value for that sink signal along with an associated driver width indication for each driver signal, and an operation type indication for the operation used to compute the result value for the sink signal. A scalability check operation is then executed on processing circuitry for one or more selected entries in the mapping table that have at least one of the sink and driver width indications specified with reference to at least one parameter. The scalability check operation comprises determining, using the operation type indication and the driver width indication for each driver signal, a driver signal identifying an expected width for the sink signal, and determining using the sink width indication a sink formula to identify the width of the sink signal. The sink formula and the driver formula are then evaluated to determine whether the presence of the at least one parameter gives rise to a scalability issue. A result file is then output identifying each sink signal that has been detected to have a scalability issue.

A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.

Embodiments are directed to a method and system for testing and optimizing integrated circuit devices. Latches within an integrated circuit device that fail to operate properly are found using observed data from a test. Thereafter, a directed graph of the layout of the integrated circuit is used to find clock controllers that feed into the latches. The clock controllers that are the most likely to be at issue are ranked, then testing can be performed to confirm that a critical path can be found. The critical path can be excluded from further power optimization to maintain the performance of the integrated circuit device. Other embodiments are also disclosed.

A computer system verifies functional test patterns for diagnostics, characterization and manufacture testing. The system generates, by a system designer, verification sequences including initial trace traces selected from a verification sequence data to test system functional design. The system includes a trace module, an emulated pattern generator module, and a test pattern verification and debug module. The trace module adds custom information to the traces to generate modified traces and the system executes the verification sequences against a device to generate traces. The trace module further processes the modified traces by parsing the captured modified traces. The system verifies data integrity and summarizes statistics of the captured traces. The emulated pattern generator module generates emulated test patterns, which are based on the output of the trace module and have independent format streams compatible with a device test port. The test pattern verification and debug module verifies the emulated test patterns.

Disclosed are a test apparatus and a testable asynchronous circuit. The test apparatus includes: a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a first selector, a second selector, a D flip-flop, and a first output end. The first input end is configured to input a data signal or a test result of a previous circuit under test; the second input end is configured to input a test excitation signal or a test result that is output by a previous test apparatus; the third input end is configured to input a clock signal; the fourth input end is configured to input a selection signal; and the fifth input end is configured to input a selection signal.

Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test. Aspects include: receiving from a system designer, via a design verification tool module, certain verification sequences configured to verify system functional design, executing the verification sequences received at a functional exerciser module against a device to generate various traces, capturing traces generated in emulation compatible format, processing traces captured via trace processor module, including parsing the traces captured, verifying data integrity of the traces captured, and summarizing statistics of the traces captured, generating, via an emulated pattern generator module, a predetermined number of emulated test patterns having tester independent format streams of data compatible with a device test port based on output of the trace processor module, and processing, via a tester specific post-processor module, the emulated test patterns to generate functional test patterns using a tester specific post-processor module.

Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.

A new low-power test compression method and design for testability (DFT) architecture are proposed for deterministic test pairs for launch-on-capture (LOC) transition fault testing by using a new seed encoding scheme, a new low-power test application procedure and a new test compression architecture. The new seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set. The low-power test compression architecture includes: (1) the LFSR established by the selected primitive polynomial and the selected number of extra variables injected to the LFSR; (2) the scan tree architecture for LOC transition fault testing; and (3) the new gating technique. A new static test compaction scheme is proposed by bitwise modifying the values of a seed and the extra variables. A new technique for test point insertion is proposed for LOC delay testing in the two-frame-circuit model, which apparently reduces test data volume.

The present disclosure relates to a system and method for performing scan chain diagnosis of an electronic design. The method may include identifying, at a computing device, at least one failing scan chain associated with the electronic design. The method may also include selecting a plurality of defect locations associated with the at least one failing scan chain, wherein the plurality of defect locations corresponds to a number of parallel patterns that a simulator is configured to process. The method may further include selecting a sliced failing pattern set and generating a plurality of copies of a pattern associated with the sliced failing pattern set, wherein each of the plurality of copies corresponds to one of the plurality of defect locations. The method may also include simulating the plurality of copies of the pattern in parallel.

An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.