Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.

Apparatuses, systems, methods, and computer program products are disclosed for stimulus generation for component-level verification. A method includes monitoring one or more internal signals for one or more components of a chip during a full-chip verification process. A method includes generating one or more stimuli for triggering one or more internal signals during verification of one or more components of a chip. Stimuli may be generated based in part on feedback from a full-chip verification process. A method includes verifying an operating state of one or more components of a chip in response to generated stimuli that trigger one or more internal signals during verification of the one or more components.

A method is provided for analyzing failure rates due to soft/hard errors in the design of a digital electronic device. The method includes creating an error injection point by introducing a fault into a code path having a plurality of levels; determining an error detection point at which the introduced fault becomes detectable; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error detection point, thereby generating a first logic cone list; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error injection point, thereby generating a second logic cone list; determining the intersection between the first and second logic cone lists; and conducting a failure rate analysis on the intersection between the first and second logic cone lists.

A semiconductor device includes a bus, first and second bus drivers that drive the bus, and a control circuit that controls the first and second bus drivers. The control circuit controls the first and second bus drivers in such a way that the first and second bus drivers supply logic signals different from each other to the bus.

An information processing apparatus includes a processor including hardware. The processor extracts neighboring nodes in two or more different extraction ranges for each node constituting input data of a graph structure. The processor calculates an anomaly score representing a degree of anomaly of the node for each extraction range based on a representation of a combination of the node and the neighboring nodes. The processor records each calculated anomaly score in a storage. The processor selects a maximum anomaly score among the anomaly scores recorded in the storage. The processor determines an anomaly node in the input data of the graph structure based on the selected maximum anomaly score. The processor outputs information of the anomaly node.

A method and a system for verifying an integrated circuit stack having a silicon photonic (SIPH) device is introduced. A single first dummy layer is added to at least one terminal of the SIPH device in a first layout of the first integrated circuit, wherein a shape of the single first dummy layer added to the at least one terminal of the SIPH device maps a shape of the at least one terminal of the SIPH device. A first layout versus schematic (LVS) check is performed on the first integrated circuit based on the single first dummy layer added to the at least one terminal of the SIPH device to verify a connection of the SIPH device in the first integrated circuit.

A system and method to increase the yield of manufactured integrated circuits by providing remedial circuit elements including alternate plane transistors, manufactured by middle of line and/or back end of line processes, to enable and disable the remedial circuit elements which provide additional circuit functions, when needed, as determined by post-manufacture testing of the integrated circuits and/or by in-operation monitoring of circuit operation. The system and method can address the distribution of the power supply and signals, such as clock signals, and/or high speed I/O signals, through problem areas resulting from sub-optimal designs, circuit aging and/or failures due to manufacturing process variations.

A system and method are disclosed for assembling a testbench for evaluating electronic systems. The method includes assembling large testbenches by using verification features associated with functional components, automatically creating component connections, and statistically checking the testbench prior to generation and simulation. The system includes a computer system that implements the method.

A method for verifying a power-management system including a controller and a plurality of power devices, wherein the controller receives a plurality of input signals to generate a plurality of control signals to control the power devices, includes: determining each of the power devices operating in a corresponding mode when the power-management operates under a power configuration; determining a target combination of the control signals when each of the power devices operates in the corresponding mode; patternlessly verifying a behavior of the controller with an input combination of the input signals for the power-management system operating under the power configuration to generate a calculated result of the control signals; comparing the calculated result to the target combination; and determining that the input combination is valid when the calculated result is equal to the target combination.

A new approach is proposed to support device under test (DUT) validation reuse across a plurality of platforms, e.g., hardware simulation, hardware emulation, and post-silicon validation. First, an inference profile used for an inference operation of an application, e.g., a machine learning (ML) application, is generated based on a set of profile configurations, a set of test parameters, and a set of randomized constraints. A plurality of math functions specified by, e.g., an architecture team, for the ML application are also statically and/or dynamically verified via block simulation and/or formal verification. An inference model for the DUT is then built based on the inference profile and the plurality of verified math functions. Finally, an inference database including one or more of stimulus, DUT configurations, input data and predicted output results is generated based on the inference model, wherein the inference database for the DUT is reusable across the plurality of platforms.