Embodiments relate to a system for translating design specifications of an electronic circuit. In one embodiment, the design specification is parsed to identify one or more sentences. From the one or more identified sentences, the system extracts semantic concepts. Additionally, for each sentence of the one or more identified sentences, the system determines whether the sentence is translatable. If a target sentence is translatable, the system generates a parse tree for the target sentence, and generates a probabilistic shift-reduce schedule for the generated parse tree. Using the generated probabilistic shift-reduce schedule and optionally the generated parse tree, the system generates code for verifying the condition specified in the target sentence. In some embodiments, to generate the code, the system parses the target sentence using the generated probabilistic shift-reduce schedule.

A digital electronic circuit (DCCT) configured for testing in accordance with a Design-for-Test (DFT) technique such as a hierarchical, compressed random access scan (CRAS-N) DFT technique and, in particular, a segmented, random access scan a (SRAS) DFT technique.

A method for debugging and a method for testing a circuit design on a programmable logic device is disclosed, making use of a parameterized configuration. A corresponding system also is disclosed.

A method and system for performing actions through testbench components present within a test environment based on a testing context is disclosed. The method includes sending, by each of a plurality of testbench components to an actions controller, an associated controllable actions packet, wherein the controllable actions packet comprises a list of controllable actions corresponding to a testbench component. The method further includes receiving, by each of the plurality of testbench components from the actions controller, an associated context-based actions control packet in response to sending. The method includes configuring each of the plurality of testbench components based on the associated context-based actions control packet. The method further includes performing, by each of the plurality of testbench components, the one or more actions present within the associated context-based actions control packet.

The present disclosure discloses an SoC chip distributed simulation and verification platform and a method, and the present disclosure relates to the field of chip verification technologies. The distributed simulation and verification platform includes component modules of an SoC chip; each module has its own verification platform, and each verification platform separately runs in a different simulation process; and virtual connections between the modules are implemented through respective verification platforms, to implement system function simulation and verification. In the present disclosure, a virtual connection technology is used to connect Testbench test platforms of the modules or IPs, to implement virtual integration of the modules or IPs, thereby completing distributed simulation and verification of a system function of the SoC chip.

A system and corresponding method captures speculative and concurrent trace-data and trace-clock information from core processing units of a System on a Chip (SOC). An interface receives trace data from at least one core processing unit, and a storage array stores the trace data in two different modes of operation. In the first mode, which occurs prior to a predetermined operating state of the SOC, the storage array operates in a circular buffer mode in which the newest trace data overwrites the oldest trace data when the storage array becomes full In the second mode, which occurs after the predetermined operating state of the SOC, the storage array operates in a FIFO mode in which the newest trace data is written into the storage array and the oldest trace data contained in the storage array is output to a debug processing core unit of the SOC.

A method implemented by computer for compressing and decompressing all the fault scenarios of a processor comprising computation units interconnected by a communication network having topology symmetries, each fault scenario corresponding to the number and the location of one or more failing computation units and the method comprises the steps of reception or determination of one or more topology symmetries; determination of the equivalent scenarios by means of said topology symmetries; each of the fault equivalence classes being associated with a resource allocation solution in terms of mapping and routing. Different developments include the determination or the application of an inference engine, of identifiers associated with the fault scenarios, of combinatorial exploration techniques, of compression rates, of reconfiguration of the processor and of classification of the processor in a range. A program product and associated systems are also described.

An integrated circuit and method for establishing scan test architecture in the integrated circuit is provided. The integrated circuit includes a plurality of circuit modules. Each circuit module includes a clock control unit, a first pipeline unit, a serialized compressed scan circuit and a second pipeline unit. The clock control unit generates a scan clock according to a test clock. The first pipeline unit converts a test input signal into first data according to the scan clock. The serialized compressed scan circuit generates second data according to the first data and the test clock. The second pipeline unit converts the second data into a test output signal according to the scan clock. The scan clock of each of the circuit modules is independent from the scan clocks of the other circuit modules, thereby reducing the difficulty and cost of timing analysis and adjustment.

A method includes determining a register-transfer level and Unified Power Format (RTL-UPF) description for a circuit that includes a plurality of RTL modules, at least two of the RTL modules being located in different power plane domains; determining a design for test (DFT) for the RTL-UPF description by adding a scan control logic and associated scan flip flops to the RTL-UPF description, thereby generating at least one power domain crossing between the at least two power plane domains, wherein the at least one power domain crossing is unprotected with respect to a floating voltage level on the at least one power domain crossing; determining an isolation cell requirement for the at least one power domain crossing; selecting an RTL-UPF isolation rule using the determined isolation cell requirement for the at least one power domain crossing; and inserting an isolation cell described by the selected RTL isolation rule into the DFT.

Power-gated domains are provided for design for test (DFT) and/or design for debug (DFX) logic units in a semiconductor chip. Power-gated domains allow power consumption to be reduced when DFT and DFD logic units are not in use. Power-gated domains can include reset features and output port power isolation.