Methods and systems for performing fault injection testing on an integrated circuit hardware design. The methods include: (a) receiving a raw fault node list identifying one or more fault nodes of the hardware design; (b) receiving information indicating a grouping of the fault nodes in the raw fault node list into a plurality of fault node groups, each fault node group comprising fault nodes that have a same effect on a failure mode of the hardware design; (c) generating a final fault node list based on the fault node groups; (d) selecting a set of fault injection parameters from the final fault node list, the set of fault injection parameters identifying at least one fault node in the final fault node list to fault; (e) performing a fault injection test on the hardware design by causing a fault to be injected into a simulation of the hardware design based on the selected set of fault injection parameters; (f) determining a result of the fault injection test; (g) storing the result of the fault injection test; and repeating (d) to (g) at least once.

The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.

A chip verification system includes a plurality of agent modules, a register model, and a scoreboard module. The register model includes a register database, a plurality of access modules, and a return module. Each access module corresponds to one of a plurality of attribute parameters. Each agent module transmits an address code of its sequence to the return module. The return module obtains, according to the received address code, an address subject and the attribute parameter corresponding to the received address code from the register database, and outputs the obtained attribute parameter. Each driver module calls, according to the received attribute parameter, the corresponding access module to perform an operation on registers of DUT circuit according to a read write command of the sequence. The scoreboard module records each performed operation to generate an operation record, and outputs a verification result according to the operation record and data in registers.

A system for optimizing scan pipelining may include a processor and a memory. The processor may generate and insert, based on prior analysis of the physical layout of the circuit, an optimized number of pipeline stages between a first block and a second block in a hardware test design, a first scan chain including at least one pipeline stage of a head pipeline stage or a tail pipeline stage. The processor may insert a plurality of flip-flops into the first scan chain. The processor may determine at least one clock to be used for the at least one pipeline stage, using the plurality of flip-flops so as to eliminate the need of a lockup element between the at least one pipeline stage and the plurality of flip-flops. The processor may generate, based on the at least one clock, a second scan chain that connects the at least one pipeline stage and the plurality of flip-flops.

A scan flip-flop includes a selection circuit, a primary latch, a secondary latch, and a data retention latch. The selection circuit selects and outputs one of functional data, first reference data, scan data, and first control data as second reference data. The primary latch receives the second reference data and outputs third reference data, whereas the secondary latch receives the third reference data and outputs second control data. The second control data is then provided to a subsequent scan flip-flop of a scan chain. The data retention latch receives one of the third reference data and the second control data, and outputs and provides the first reference data to the selection circuit. The first reference data corresponds to functional data retained in the scan flip-flop during a structural testing mode associated with the scan chain.

A test and measurement system for parallel waveform analysis acquires waveforms resulting from performing tests on a device under test (DUT) and performs, at least partially in parallel, respective analyses of the waveforms resulting from performing tests on the DUT. The system also acquires a first waveform resulting from performing a first test with an oscilloscope on a DUT and performs analysis of the first waveform at least partially in parallel with acquiring a second waveform. Additionally, the system tracks a plurality of testing assets using inventory information of a plurality of testing equipment on the network and enables remote users to access equipment logs and results of the respective analyses of the waveforms stored on a cloud computing system for performance of analytics.

A core partition circuit comprises a first decompression circuit, a second decompression circuit, a first switching circuit, an wrapper scanning circuit, a first compression circuit, a second compression circuit and a second switching circuit. The first and second decompression circuits decompress an input signal. The first switching circuit outputs the output signal of the first decompression circuit or the second decompression circuit according to a first control signal. The wrapper scanning circuit receives the output signal of the first decompression circuit or the second decompression circuit to scan the internal or the port of the core partition circuit. The first and second compression circuits respectively compress the internal logic and the port logic of the core partition circuit. The second switching circuit outputs the compressed internal logic or port logic of the core partition circuit according to the first control signal.

Various embodiments provide for testing a transmitter with interpolation, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer over a plurality of different interpolation phase positions of a phase interpolator; and using a pattern checker to error check the sampled data over the plurality of different interpolation phase positions to determine whether the data transmission test passes.

Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.