A computer executable tool analyzes a gate-level netlist and uses an analysis result for accelerating a timing-accurate gate-level logic simulation via a parallel processing. The analysis identifies the following elements in the gate-level netlist: (1) netlist wires at partition boundaries for a value propagation; (2) netlist wires whose activities should be suppressed for a better performance; and (3) upstream FFs for partition boundaries to reduce a synchronization overhead. This information is then used to improve a parallel simulation performance.

An embodiment herein provides a method for implementing verification IP for pre-silicon functional verification of a layered protocol. The method includes generating serially connected layer blocks. A layer block includes modular components that may be enabled or disabled to change a functionality of the layer block. The modular components include a layer core, a stimulus handler, one or more transmit routers and one or more receive routers. The layer core implements the complete functionality of the layer block. The stimulus handler drives input stimulus transactions into the layer core of the layer block. The one or more transmit routers routes one or more transmit core transactions from the layer core to the connected succeeding layer block. The one or more receive routers routes one or more receive core transactions from the succeeding layer block to the layer core.

A regression suite apparatus for semiconductor IP having a plurality of functional blocks provides a knowledge graph defining, for each pair of first and second functional blocks, an indication of whether the second functional block depends on the first functional block; in case of a dependency, the knowledge graph comprises a weight representing a degree of dependency of the second functional block on the first functional block; an input for indicating functional blocks changed in an updated design; a selector arranged to select a subset of the tests by selecting numbers of tests of each of a plurality of different levels, wherein a first level selects tests corresponding to an input functional block and a second level selects tests corresponding to the input functional block in combination with second level blocks dependent on the input functional block; and apparatus for running the selected subset of tests on the updated design.

Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

A computing system implementing a functional safety validation tool to simulate a circuit design having a digital portion and an analog portion, and inject a fault into the digital portion of a simulated circuit design, which propagates towards alarm logic configured to detect the injected fault. When the injected fault propagates to a boundary between the digital portion and the analog portion, the functional safety validation tool can perform a parallel simulation of the analog portion, which propagates the injected fault from the boundary through the analog portion to an output. The functional safety validation tool can determine whether the analog portion of the circuit design suppresses the injected fault based on a value at the output. The functional safety validation tool can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic based on whether the injected fault was suppressed.

A method is provided for analyzing failure rates due to soft/hard errors in the design of a digital electronic device. The method includes creating an error injection point by introducing a fault into a code path having a plurality of levels; determining an error detection point at which the introduced fault becomes detectable; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error detection point, thereby generating a first logic cone list; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error injection point, thereby generating a second logic cone list; determining the intersection between the first and second logic cone lists; and conducting a failure rate analysis on the intersection between the first and second logic cone lists.

A new low-power test compression method and design for testability (DFT) architecture are proposed for deterministic test pairs for launch-on-capture (LOC) transition fault testing by using a new seed encoding scheme, a new low-power test application procedure and a new test compression architecture. The new seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set. The low-power test compression architecture includes: (1) the LFSR established by the selected primitive polynomial and the selected number of extra variables injected to the LFSR; (2) the scan tree architecture for LOC transition fault testing; and (3) the new gating technique. A new static test compaction scheme is proposed by bitwise modifying the values of a seed and the extra variables. A new technique for test point insertion is proposed for LOC delay testing in the two-frame-circuit model, which apparently reduces test data volume.

The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.

A method for generating a validation test for testing an electronic design may include using a processor, analyzing a plurality of actions of a validated scenario to identify an executable corresponding to each of the actions and to identify one or a plurality of variables referred to by each of the actions; using a processor, identifying actions in said plurality of actions that correspond to different executables of the identified executables but refer to a same variable of said one or a plurality of variables that is to be written to or read from a shared memory assigned to the different executables; and using a processor, generating a test code for the validated scenario that includes one or a plurality of access protection commands to manage access by the identified actions that correspond to the different executables and refer to the same variable.

Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.