At least one processor core has debug and non-debug modes of operation. Debug control circuitry controls operation of the at least one processor core when in the debug mode. On power up of a given processor core, the core checks a debug status value stored in a debug status storage element. When the debug status value has a first value, a debug connect sequence of messages is exchanged with the debug control circuitry over a debug interface to determine whether the given processor core should operate in the debug mode or the non-debug mode, and the debug status value is set to a second value when it is determined that the given processor core should operate in the non-debug mode. When the debug status value has the second value, the given processor core omits initiating the debug connect sequence and determines that it should operate in the non-debug mode.

Disclosed approaches involve at least one processor executing a program and a debug interface circuit coupled to the processor. The debug interface circuit is configured to transmit first trace data from the first processor. A debug access port is coupled to the debug interface circuit. A fault detection circuit is coupled to the debug access port and is configured to receive the first trace data via the debug access port and compare the first trace data to second data. The fault detection circuit generates an error signal to the first processor in response to a discrepancy between the first trace data and the second data.

An error-handling processing circuit and system are provided. The system can receive an error signal, such as an interrupt, and decouple (e.g., by a gate signal) a functional clock from a processing block, in some instances effectively halting the processing block's operation. This can prevent a cascade of interdependent errors, thereby avoiding producing redundant or confusing error information. The system can include the processing block, a debug clock not coupled to the processing block, and a data block (e.g., a register file) coupled to the debug clock and to an external input/output interface. The data block can be configured to continue receiving a clock signal via a multiplexer from the debug clock without disruption after the functional clock is decoupled, enabling the data block to remain operational for debugging.

A post-fabrication debug and on-line error checking framework for 2D- and 3D-ICs with integrated memories is described. A design-for-debug (DfD) architecture can include, for an IC with on-chip memory, a debug module connected to a functional bus of the IC. The debug module receives trace data for an interval, generates compact signatures based on the received data, and compares these signatures to expected signatures. Intervals containing erroneous trace data can be identified by the debug module and stored in on-chip memory. A single iteration of signal tracing for debug testing between automated test equipment and the IC is possible.

A radio frequency transceiver device comprises a control register unit including one or more registers and a central processing unit arranged to access the one or more registers via a memory bus. The device also comprises a sequencer module comprising one or more configuration registers connected to the central processing unit via a control bus and also comprises one or more trigger inputs. A sequencer memory module is connected to the sequencer module and is arranged to store one or more read/write commands comprising instructions to read from and/or write to the registers within the control register unit. The sequencer module is arranged such that upon receiving a trigger event via at least one of the one or more trigger inputs, it executes the one or more read/write commands.

The invention relates to a real-time oscilloscope with a built-in time domain reflectometry (TDR) and/or time-domain transmission (TDT) function for measurements of a device under test (DUT). The real-time oscilloscope comprises at least one built-in generator and at least one real-time measurement channel. The built-in generator is in communication with the real-time measurement channel and the device under test (DUT) and is configured to generate incident signals. The real-time measurement channel is configured to capture incident signals transmitted to and reflected by and/or transmitted by the device under test (DUT).

A system and method for time stamp synchronization are disclosed. In one embodiment, first and second devices are provided. The second device receives a first time stamp of the first device, wherein the first time stamp was generated in response to a time stamp synchronization event common to the first and second devices; generates a second time stamp of the second device in response to the time stamp synchronization event, wherein the first and second time stamps are in different time domains; and correlates the first and second time stamps, wherein correlating the first and second time stamps provide a relationship between the time domains because the first and second time stamps were both generated with respect to the same time stamp synchronization event common to the first and second devices.

Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

Techniques and mechanisms for providing on-chip link control functionality to facilitate emulation of a communication. In an embodiment, an integrated circuit (IC) chip includes a physical layer (PHY) which supports communication compatible with a high-speed serial interface standard. A link controller of the IC chip is coupled between the PHY and an interconnect architecture which variously couples a host and other resources of the IC chip to each other. A test controller of the IC chip signals a test mode to implement a loopback path of the link controller in lieu of one or more functional paths for communication with the PHY. In another embodiment, signal output by the loopback path emulate a communication from a resource other than the test controller.

A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.