The present invention discloses a test device for testing an integrated circuit. An embodiment of the test device includes an on-chip-clock controller (OCC), a pulse debugging circuit and a register circuit. The OCC is configured to generate an output clock according to an input clock, in which the output clock is for testing a circuitry under test (CUT) that is included in the test device. The pulse debugging circuit is configured to generate a pulse record according to a pulse number of the output clock, in which the pulse record is used to find out whether a test status dependent upon the output clock is abnormal. The register circuit is configured to store and output the pulse record according to a reliable clock.

An integrated circuit (IC) includes a plurality of intellectual properties (IPs), each of the plurality of IPs includes a test logic. A first memory controller provides user data received from at least one of the plurality of IPs to a first memory in a first operation mode. A scanner gathers debugging data from the test logics of the plurality of IPs in a second operation mode. And a second memory controller receives the debugging data from the scanner and provides the debugging data to the first memory in the second operation mode.

An example of a system includes a host interface, a set of non-volatile memory cells assigned a first logical address range, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits are configured to generate debug data and send the debug data through the host interface in response to a command received through the host interface. The command is directed to a second logical address range, the second logical address range assigned exclusively for debug data.

A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.

In accordance with embodiments of the present disclosure, an information handling system may include a host system with information handling resources, a management controller configured to provide out-of-band management of the information handling system, and a debugging circuit. The debugging circuit may receive a plurality of serial data streams from the management controller and the plurality of information handling resources, and provide access to at least a subset of the plurality of serial data streams to a debugging information handling system via a wireless interface.

The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.

A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip. The method comprises the debug unit collecting debug data of the peripheral circuit and outputting the debug data in a message stream. The debug unit receives a debug reconfiguration command. The debug unit transmits an indication of the current debug configuration, then reconfigures the current debug configuration to a new debug configuration in accordance with the debug reconfiguration command, then transmits an indication of the new debug configuration. The indication of the current debug configuration and the indication of the new debug configuration are transmitted adjacent to the debug data in the message stream.

A scan data control apparatus includes a trigger circuit, a scan sequencer, a shift register, and a transmitter. The trigger circuit is configured to receive a trigger signal, detect a malfunction of a system and output a scan mode start signal and a scan mode end signal. The scan sequencer is configured to output scan enable signals corresponding to a CPU and a master to the CPU and the master. The shift register is configured to receive scan data of the CPU and the master from the CPU and the master. The transmitter is configured to receive the scan data of the CPU and the master and output the scan data to a memory.

Diagnostic operations upon a target apparatus 2 having a target transaction master 8 which initiates memory transactions with one or more target transaction slaves 12, 14, 16 are provided by halting operation of the target transaction master 8 while permitting continued operation within the target apparatus 2 of at least some of the target transaction slaves 12, 14, 16. Opening state data representing an operating state of the target transaction master 8 is transferred to a model transaction master 32. Further operation of the target transaction master 8 is emulated using the model transaction master 32 using the opening state data. Diagnostic operations are performed upon the model transaction master 32. When the model transaction master 32 emulates initiation of a memory transaction with a memory address mapped to one of the target transaction slaves 12, 14, 16, this initiates the memory transaction to be performed with the target apparatus 2. Pages of stored values from the memory address space of the target apparatus 2 may be cached within the emulation.