Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a debug and test access port to debug and test the device circuit, and a switching circuit to switch a debug and test mastership between the debug and test access port and a data access port to the device circuit that is not dedicated to debug and test.

A server Joint Test Action Group (JTAG) component adaptive interconnection system and method. The system includes a JTAG master device, a programmable device, and a plurality of JTAG components. The programmable device is configured to simulate JTAG timing according to a JTAG protocol and test JTAG channels of the JTAG components connected to the programmable device one by one. The programmable device connects in series a Test Data Output (TDO) signal of a previous JTAG component with a Test Data Input (TDI) signal of a next JTAG component in the programmable device, connects a TDI signal of a first JTAG component with a TDI signal of the JTAG master device, and connects a TDO signal of a last JTAG component with a TDO signal of the JTAG master device, so as to form a JTAG interconnection chain.

An apparatus for electrically coupling an electrical interface of a unit under test with a debugging component includes a bracket assembly having a socket configured to electrically couple with the electrical interface, a baseplate assembly configured to secure the unit under test on a plate, a crane assembly coupled to the bracket assembly, and a cable assembly. The crane assembly is configured to enable movement of the socket relative to the electrical interface in each of a horizontal direction, a vertical direction, and an angular direction; and secure the socket in place relative to the electrical interface while applying a force by the socket against the electrical interface. The cable assembly is associated in part with the bracket assembly and is configured to electrically couple with the socket at a first end and with the debugging component at a second end.

A digital device comprising a functional unit, a real-time performance information unit, and a monitoring unit is described. The real-time performance information unit provides real-time performance information about the functional unit. The real-time performance information unit enables the local host device to retrieve the real-time performance information from the real-time performance information unit. The monitoring unit retrieves the real-time performance information from the real-time performance information unit. The monitoring unit has a network interface for connecting to a network. The monitoring unit is arranged to upload the real-time performance information to the network via the network interface. A method of operating the digital device is also described.

Systems and methods for improving system debugging using finite state machines are described. In one embodiment, the systems and methods includes selecting, by a first multiplexor, a period of a timer tick for one or more blocks of a system on a chip (SoC), comparing, by a first comparator, a current state of the one or more blocks to a previous state of the one or more blocks, and receiving, by a finite state machine (FSM), the result from the first comparator as a first input, receiving a pulse based on the selected period of the timer tick from the first multiplexor as a second input, and based on the first and second inputs generating an output indicating whether the current and previous states remain unchanged after a time of at least two timer ticks. In one embodiment, a result from the first comparator indicates whether the current state equals the previous state of the one or more blocks.

Aspects disclosed in the detailed description include high-frequency signal observations in electronic systems. In this regard, a high-frequency signal observation circuit is provided in an electronic system to enable high-frequency signal observations. In one aspect, the high-frequency signal observation circuit comprises an observation signal selection circuit. The observation signal selection circuit is programmably controlled to select an observation signal among a plurality of electronic input signals (e.g., control signals) received from the electronic system. In another aspect, the high-frequency signal observation circuit is configured to utilize a bypass data path, which is routed around serializer/deserializer (SerDes) logic in the electronic system, to output the observation signal for observation. By programmably selecting the observation signal and outputting the observation signal via the bypass data path, it is possible to examine accurately any high-frequency signal (e.g., high-frequency clock signal) in the electronic system with minimized delay and/or degradation in the high-frequency signal.

Systems, methods, and apparatuses to perform an operation comprising receiving an indication of a first error in a processor, identifying a first control signal, of a plurality of control signals in a debug bus, associated with the error, wherein each of the plurality of control signals are coupled to one of a plurality of input ports of a multiplexer, and changing a configuration state of the multiplexer to output the first control signal to a trace array.

A circuit for implementing a scan chain in an integrated circuit having a clock domain crossing is described. The circuit comprises a first dual-edge storage circuit configured to receive an input signal at a scan input and to receive a first clock signal in a first clock domain at a clock input; a storage element having a data input configured to receive an output of the first dual-edge storage circuit; a second dual-edge storage circuit configured to receive an output of the storage element at a scan input and to receive a second clock signal in a second clock domain at a clock input; and a pulse generator configured to provide, to a clock input of the storage element, a pulse signal having a pulse width selected to enable the second dual-edge storage element to store the output of the first dual-edge storage element.

A system on a chip including a processor and an in-circuit emulator located within the processor. The processor is to perform processing functions associated with controlling operation of the system on a chip. The in-circuit emulator includes instrumentation logic to take over controlling the operation of the SOC from the processor, perform debugging and emulation functions, and output data including results of the debugging and emulation functions. A frame capture module is to package the data including the results of the debugging and emulation functions into frames having a parallel format. A serializer is to convert the frames from the parallel format to a serial format and output the frames having the serial format from the system on a chip.

Techniques for secure debugging and monitoring are presented. An end user requests a secure token for logging information with a remote service. A secure monitoring and debugging token service provides the secure token. The remote service validates the secure token and configures itself for capturing information and reporting the captured information based on the secure token.