An information processing apparatus includes an integrated circuit that is capable of reconfiguring a logic circuit, that executes data processing, and that is capable of acquiring signal data from an acquisition target position set in a circuit portion where the data processing is performed and outputting the signal data, a change unit that changes the acquisition target position in the circuit portion where the data processing of the integrated circuit is performed in a case where an error is generated in the data processing of the integrated circuit, and a control unit that causes the integrated circuit to re-execute the data processing in which the error is generated, after the acquisition target position is changed.

Systems and techniques of the present disclosure may provide remote debugging of an integrated circuit (IC) device while preventing unauthorized access of device intellectual property (IP). A system may include an IC device that generates an encrypted session key and an interface that enables communication between the IC device and a remote debugging site. The interface may enable the IC device to send the encrypted the encrypted session key to initiate a remote debug process, receive an acknowledgement from the remote debugging session, and authenticate the acknowledgement. Further, the interface may enable to the IC device to initiate a secure debug session between the IC device and the remote debugging site.

Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

Provided are scan device and method of diagnosing scan chain fault. The scan device for diagnosing a fault includes a scan partition including a plurality of scan chains which include path control scan flipflops connected to scan flipflops in cascade. In the scan partition, connection paths of the scan flipflops are controllable. The connection paths of the path control scan flipflops are controlled to detect a position of a fault such that a fault range in the scan partition is reduced to diagnose the fault.

The invention discloses an extended joint test action group based controller and a method for functional debugging using the extended joint test action group based controller. The object of the invention to lower the power dissipation (dynamic and leakage) but providing the same functionality of the testing and debugging procedures at the same time will be solved by an extended joint test action group (JTAG) controller for testing flip-flops of a register of an integrated circuit (IC) using a design for testing scan infrastructure on the IC which comprises at least one scan chain, wherein an external debugger is connected to the design for testing scan infrastructure via the JTAG controller which is extended by a debug controller, whereas a feedback loop is formed from an output of the scan chain to an input multiplexer of the scan chain which is activated according to the extended JTAG controller.

An apparatus includes one or more functional circuits, a debug circuit configured to implement one or more debug features for the one or more functional circuits, and a validation circuit. The validation circuit is configured to receive a request to access debug features, and to send an identification value corresponding to the apparatus. The validation circuit is further configured to receive a certificate generated by a server computer system, the certificate including encoded debug permissions, and to decode the debug permissions using the identification value. Using the decoded debug permissions, the validation circuit is further configured to enable one or more of the debug features.

The invention relates to a communication method and its system between interconnected die and DSP/FPGA. The method includes multiple data interfaces. Each data interface is provided with a different protocol conversion module, wherein the data interface communication includes data input conversion and data output conversion; wherein during input conversion, the external data is converted into a unified data protocol format by protocol conversion module, which is transmitted to the network on die for unified data transmission; wherein during output conversion, the internal data is converted into different data protocol formats by protocol conversion module, and then enters different data interfaces and is transmitted to the DSP/FPGA. This method allows each device and component to be connected to the multi-die system in any form, which improves the flexibility of the system.

An on-chip debugging device and method is provided. The on-chip debugging device includes: an external interface module configured for outputting chip debugging state information to an external debugger and receiving a control instruction of the external debugger; a debugging mode control module configured for setting a to-be-sampled type of a specified chip internal signal and setting a debugging trigger condition according to the debugging configuration of the external debugger or the internal CPU; a debugging monitor module configured for sampling and recording the internal signal of the chip of the specified type so as to identify the running state of the chip; and a debugging information processing module configured for storing the running state of the chip in an internal debugging memory and sending it to the external debugger by the external interface module or sending it to the internal CPU via an internal bus. The on-chip debugging functions which are relatively simple, occupy less resources and have more powerful functions can be realized by the device and the method.

Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

Systems and methods are disclosed for secure debug architecture. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions; a debug interface comprising two or more conductors with input/output drivers configured to, when enabled, transmit and receive signals between the processor core and an external host device via the two or more conductors; and wherein the integrated circuit is configured to: receive a request from a host device for access to the integrated circuit via the debug interface; responsive to the request, generate a random number; transmit the random number from the integrated circuit to the host device via the debug interface; receive, from the host device via the debug interface, input data that has been encrypted using the random number as a key; and decrypt the input data using the random number as a key.