The invention discloses an interface system for an interconnected die and an MPU and a communication method thereof. The system comprises a data interface, an interrupt interface, and a debugging interface; the data interface comprises an SPI interface, a DDR data interface, and a DMA control interface; the interrupt interface is used for receiving an interrupt data packet from the network and parsing the interrupt data packet to obtain a pulse interrupt input required by the MPU; the debugging interface comprises a JTAG-Core debugging interface, which is used for receiving a debugging data packet from the network and translating the debugging data packet into a JTAG protocol for MPU debugging. The invention realizes the expansion of the master device MPU in the high-performance information processing microsystem and the high-speed communication between the master device and the interconnected dies.

A circuit debug apparatus for debugging an integrated circuit that causes a functional fault may include a processor configured to extract a scan pattern of a scan chain of the integrated circuit while the integrated circuit is in a scan mode. The scan pattern includes a plurality of logic states for a corresponding plurality of logic circuits of the integrated circuit. The processor may also be configured to apply a modified scan pattern to the integrated circuit while the integrated circuit is in the scan mode, where the modified scan pattern includes a test pattern configured to eliminate the functional fault. The processor may be further configured to determine whether the integrated circuit with the modified scan pattern produces the functional fault while the integrated circuit is in a functional mode.

Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

A debug support device includes: a root device extraction unit that extracts, from a sequence program that includes a circuit block including a plurality of devices, a result device on the basis of an association between a factor device that contributes to determination of a value of another device and the result device having the value determined by the factor device; a related device retrieval unit that retrieves, as a related device, each and every one of the factor device(s) that determines the value of the result device; and a display control unit that outputs group information to a display device. The group information is information on a group, associating the result device, the value of the result device, the related device, and a value of the related device.

The present invention provides a reliable method and arrangement for boundary scan testing and debugging newly manufactured multi-chip modules (MCMs) made to identical design specifications with no Known Good Die therein. Advantageously, a first and a second MCM are temporarily linked in tandem for boundary scan testing through a motherboard and daisy-chaining their internal dice, and interlinking the corresponding boundary scan cells of the identical dice of the first and second MCM to (1) run self-test on individual MCMs and mutual test on the MCMs connected in tandem in order to generate an extended Truth Table that includes responses from an array of combined netlists of the first and second MCMs, and (2) to diagnose mismatched bits in the extended Truth Table using a Boundary Scan Diagnostics software so as to identify defects in the first and second MCMs.

In an embodiment, an input-output (IO) device may include an IO controller and a debug controller. The IO controller may process IO data packets. The debug controller may be to: receive a first debug packet from a host system via an in-band connection, process the first debug packet to extract a command generated by the host system, and execute the extracted command to debug the IO device. Other embodiments are described and claimed.

Disclosed approaches for controlling debug access to an integrated circuit (IC) device include receiving a debug packet by a debug interface circuit of the IC device. The debug interface circuit authenticates the debug packet in response to the debug packet having a command code that specifies enable debug mode or a command code that specifies disable debug mode. In response to the debug packet passing authentication and the command code specifying enable, the debug interface circuit enables debug mode of the IC device. In response to the debug packet passing authentication and the command code specifying disable, the debug interface circuit disables the debug mode of the IC device. In response to the debug packet failing authentication, the debug interface circuit rejects the debug packet.

An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.